XR16L78464-TQFP EXAR [Exar Corporation], XR16L78464-TQFP Datasheet - Page 29

• Manufacturer Part Number: XR16L78464-TQFP
• Description: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
• Manufacturer: EXAR [Exar Corporation]

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REV. 1.2.0
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ISR[0]: Interrupt Status
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
4.4.1, Interrupt Generation:” on page 29
P
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit-7 and selection on MCR bit-2.
RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit-6 and selection on MCR bit-2.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
Interrupt Generation:
Interrupt Clearing:
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
EGISTER
T
IT
0
0
1
0
0
0
0
0
ABLE
-3
13: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
and
NTERRUPT
B
“Section 4.4.2, Interrupt Clearing:” on page 29
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
29
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default)
P
RIORITY
S
L
OURCE OF THE INTERRUPT
EVEL
Table
for details.
13). See
+
XR16L784
“Section