XR16L78464-TQFP EXAR [Exar Corporation], XR16L78464-TQFP Datasheet - Page 9

• Manufacturer Part Number: XR16L78464-TQFP
• Description: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
• Manufacturer: EXAR [Exar Corporation]

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REV. 1.2.0
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for channel ‘N’ with the following equation(s).
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO
and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
O
2.7
2.7.1
2.7.2
UTPUT
MCR Bit-7=1
T
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
115.2k
230.4k
ABLE
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
4: T
YPICAL DATA RATES WITH A
O
UTPUT
Table 4
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
shows the standard data rates available with a 14.7456 MHz crystal or external
Clock (Decimal)
D
IVISOR FOR
2304
14.7456 MH
384
192
96
48
24
12
6
4
2
1
16x
D
9
IVISOR FOR
Z CRYSTAL OR EXTERNAL CLOCK AT
Clock (HEX)
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
900
180
C0
0C
60
30
18
06
04
02
01
16x
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
WHEN
WHEN
8XMODE-
8XMODE-
V
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
16X S
30
18
06
04
02
01
(HEX)
BIT
BIT
N
N
AMPLING
IS
IS
XR16L784
D
0
1
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)