WM8985_07 WOLFSON [Wolfson Microelectronics plc], WM8985_07 Datasheet - Page 101

• Manufacturer Part Number: WM8985_07
• Description: Multimedia CODEC With Class D Headphone and Line Out
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Pre-Production
w
35 (23h)
36 (24h)
37 (25h)
38 (26h)
REGISTER
ADDRESS
3:0
8:4
3
2:0
8:5
4
3:0
8:6
5:0
8:0
BIT
ALCATK
NGEN
NGTH
PLLPRESCALE
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
LABEL
0010
0010
00000
0
000
0000
0
1000
000
01100
010010011
DEFAULT
0000
0001
0010
… (time doubles with every step)
1010
ALC attack (gain ramp-down) time
(ALCMODE == 0)
0000
0001
0010
… (time doubles with every step)
1010
or
higher
ALC attack (gain ramp-down) time
(ALCMODE == 1)
0000
0001
0010
… (time doubles with every step)
1010
Reserved. Initialise to 0
ALC Noise gate function enable
1 = enable
0 = disable
ALC Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
Reserved. Initialise to 0
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input to PLL
Integer (N) part of PLL input/output frequency
ratio. Use values greater than 5 and less than
13.
Reserved. Initialise to 0
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Fractional (K) part of PLL1 input/output
frequency ratio (treat as one 24-digit binary
number).
Per step
90.8us
181.6us
363.2us
93ms
Per step
104us
208us
416us
106ms
Per step
22.7us
45.4us
90.8us
23.2ms
DESCRIPTION
Per 6dB
726.4us
1.453ms
2.905ms
744ms
Per 6dB
832us
1.664ms
3.328ms
852ms
Per 6dB
182.4us
363.2us
726.4us
186ms
90% of range
5.26ms
10.53ms
21.06ms
5.39s
90% of range
6ms
12ms
24.1ms
6.18s
90% of range
1.31ms
2.62ms
5.26ms
1.348s
PP, Rev 3.5, January 2007
Input Limiter/
Automatic
Level Control
(ALC)
Input Limiter/
Automatic
Level Control
(ALC)
Input Limiter/
Automatic
Level Control
(ALC)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
REFER TO
WM8985
101