WM8985_07 WOLFSON [Wolfson Microelectronics plc], WM8985_07 Datasheet - Page 39

• Manufacturer Part Number: WM8985_07
• Description: Multimedia CODEC With Class D Headphone and Line Out
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Pre-Production
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Table 14 ADC Control
SELECTABLE HIGH PASS FILTER
Table 15 ADC Enable Control
Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1)
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit.
ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0.
The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order,
with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a
cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are
shown in Table 16.
Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate
(SR) is enabled by register bits R7[1:3].
HPFCUT
[2:0]
000
001
010
011
100
101
110
111
R14 (0Eh)
ADC Control
R14 (0Eh)
ADC Control
REGISTER
ADDRESS
REGISTER
ADDRESS
102
131
163
204
261
327
408
82
8
6:4
7
8
SR=101/100
BIT
0
1
3
BIT
11.025
113
141
180
225
281
360
450
563
ADCLPOL
ADCRPOL
ADCOSR128
HPFCUT
HPFAPP
HPFEN
LABEL
LABEL
122
153
156
245
306
392
490
612
12
The oversampling rate of the ADC can be adjusted using the
102
131
163
204
261
327
408
16
82
000
0
1
DEFAULT
SR=011/010
0
0
0
DEFAULT
fs (kHz)
22.05
113
141
180
225
281
360
450
563
Application mode cut-off frequency
See Table 16 for details.
Select audio mode or application mode
0 = Audio mode (1
1 = Application mode (2
HPFCUT)
High Pass Filter Enable
0 = disabled
1 = enabled
122
153
156
245
306
392
490
612
24
ADC left channel polarity adjust:
0 = normal
1 = inverted
ADC right channel polarity adjust:
0 = normal
1 = inverted
0 = 64x (lower power)
1 = 128x (best performance)
ADC oversample rate select:
102
131
163
204
261
327
408
32
82
DESCRIPTION
DESCRIPTION
SR=001/000
PP, Rev 3.5, January 2007
44.1
st
113
141
180
225
281
360
450
563
order, fc = ~3.7Hz)
nd
order, fc =
122
153
156
245
306
392
490
612
48
WM8985
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