WM9713L_06 WOLFSON [Wolfson Microelectronics plc], WM9713L_06 Datasheet - Page 16

• Manufacturer Part Number: WM9713L_06
• Description: AC 97 Audio + Touchpanel CODEC
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM9713L
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Clock mode and division ratios are controlled by register 44h as shown in Table 2.
Table 2 Clock Muxing and Division Control
INTERNAL CLOCK FREQUENCIES
The internal clock frequencies are defined as follows (refer to Figure 2):
44h
REGISTER
ADDRESS
AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz.
HIFI CLK – for HIFI playback at 48ks/s HIFI CLK = 24.576MHz. See Table 3 for voice only
playback.
Voice DAC CLK – see Table 3 for sample rate vs clock frequency.
14:12
11:8
7
5:3
2
1
0
BIT
S
S
CLKSRC
PENDIV
CLKBX2
CLKAX2
CLKMUX
EXT
EXT
LABEL
[6:4]
[3:0]
000 (div 1)
0000 (div 1)
1 (ext clk)
000 (div 16)
0 (Off)
0 (Off)
0 (MCLKA)
DEFAULT
Defines clock division ratio for Hi-fi:
DSP, ADCs and DACs
000: f
001: f/2
...
111: f/8
Defines clock division ratio for PCM
interface and voice DAC in external clock
mode only:
0000: f
0001: f/2
…
1111: f/16
Selects between PLL clock and External
clock
0: PLL clock
1: external clock
Sets AUXADC clock divisor
000: f/16
001: f/12
010: f/8
011: f/6
100: f/4
101: f/3
110: f/2
111: f
Clock doubler for MCLKB
Clock doubler for MCLKA
Selects between MCLKA and MCLKB
(N.B. On power-up clock must be present
on MCLKA and must be active for 2 clock
cycles after switching to MCLKB)
0: SYSCLK=MCLKA
1: SYSCLK=MCLKB
DESCRIPTION
PP Rev 3.0 June 2006
Pre-Production
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