WM9713L_06 WOLFSON [Wolfson Microelectronics plc], WM9713L_06 Datasheet - Page 19

• Manufacturer Part Number: WM9713L_06
• Description: AC 97 Audio + Touchpanel CODEC
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Pre-Production
DIGITAL INTERFACES
AC97 INTERFACE
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PLL REGISTER PAGE ADDRESS MAPPING
The clock division control bits S
register 46h using a sub-page address system. The 3 bit pager address allows 8 blocks of 4 bit data
words to be accessed whilst the register address is set to 46h. This means that when register
address 46h is selected a further 7 cycles of programming are required to set all of the page data
bits. Control bit allocation for these page addresses is described in Table 6.
Table 6 Pager Control Bit Allocation
Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 7).
Table 7 PLL Powerdown Control
The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface.
The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and
RESETB) and is the sole control interface with access to all data streams on the device except for
the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMFS, PCMDAC
and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo
ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by
mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM
interface.
INTERFACE PROTOCOL
The WM9713L uses an AC’97 interface for both data transfer and control. The AC-Link has 5 wires:
111
110
101
100
011
010
001
000
26h
3Ch
N.B. both PR5 and PLL must be asserted low before PLL is enabled
REGISTER
ADDRESS
ADDRESS
PAGE
SDATAIN (pin 8) carries data from the WM9713L to the controller
SDATAOUT (pin 5) carries data from the controller to the WM9713L
BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and
supplied to the controller.
SYNC is a synchronization signal generated by the controller and passed to the
WM9713L
RESETB resets the WM9713L to its default state
31:28
27:24
23:22
21:20
19:16
15:12
11:8
7:4
3:0
13
9
BIT
BIT
S
S
Reserved
K[21:0]
PR5
PLL
PLL
PLL
LABEL
LABEL
[6:4]
[3:0]
PLL
[6:0] and the PLL fractional N division bits are accessed through
0h
0h
0h
0h
0h
0h
0h
0h
0h
1 (Off)
1 (Off)
DEFAULT
DEFAULT
Clock division control bus S
divider reads this control word if PLL is
enabled. Bits [6:4] and [3:0] have the same
functionality as 44h [14:12] and [11:8]
respectively
Reserved bits
Sigma Delta Modulator control word for
fractional N division. Division resolution is
1/22
Internal clock disable (active high)
PLL powerdown (active high)
2
DESCRIPTION
DESCRIPTION
PP Rev 3.0 June 2006
PLL
WM9713L
[6:0]. Clock
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