WM9713L_06 WOLFSON [Wolfson Microelectronics plc], WM9713L_06 Datasheet - Page 94
![no-image](/images/no-image-200.jpg)
WM9713L_06
Manufacturer Part Number
WM9713L_06
Description
AC 97 Audio + Touchpanel CODEC
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
1.WM9713L_06.pdf
(108 pages)
- Current page: 94 of 108
- Download datasheet (2Mb)
42h
44h
46h
WM9713L
Register 42h controls power-up conditions for output PGAs.
Register 44h controls clock division and muxing.
Register 46h controls PLL clock generation.
w
REGISTER
REGISTER
REGISTER
ADDRESS
ADDRESS
ADDRESS
6
5
4
3
2
1
0
14:1
2
11:8
7
5:3
2
1
0
15:1
2
11
10
9
8
6:4
3:0
BIT
BIT
BIT
MONO
SPKL
SPKR
HPL
HPR
OUT3
OUT4
S
S
CLKSRC
PENDIV
CLKBX2
CLKAX2
CLKMUX
N[3:0]
LF
SDM
DIVSEL
DIVCTL
PGADDR
PGDATA
EXT
EXT
LABEL
LABEL
LABEL
[6:4]
[3:0]
0 (Off)
000 (div 1)
0000 (div 1)
0000
0 = off
0 (Off)
0 (Off)
0 (Off)
0 (Off)
0 (Off)
0 (Off)
1 (ext clk)
000 (div 16)
0 (Off)
0 (Off)
0 (MCLKA)
0
0 = off
0
000
0000
DEFAULT
DEFAULT
DEFAULT
Enables fast power for MONO output
Enables fast power for SPKL output
Enables fast power for SPKR output
Enables fast power for HPL output
Enables fast power for HPR output
Enables fast power for OUT3 output
Enables fast power for OUT4 output
Defines clock division ratio for Hi-fi block: 000=f;
001=f/2; ... ; 111=f/8
Defines clock division ratio for voice DAC clock:
0000=f; 0001=f/2; … ; 1111=f/16
Selects between PLL clock and External clock
Sets AUXADC clock divisor: 000=f/16; 001=f/12;
010=f/8; 011=f/6; 100=f/4; 101=f/3; 110=f/2; 111=f
Clock doubler for MCLKB
Clock doubler for MCLKA
Selects between MCLKA and MCLKB (N.B. On
power-up clock must be present on MCLKA and
must be active for 2 clock cycles after switching to
MCLKB)
PLL integer division control (must be set between 5-
12 for integer N mode)
Allows PLL operation with low frequency input
clocks (< 8.192MHz)
Sigma Delta Modulator enable. Allows fractional N
division
Enables input clock to PLL to be divided by 2 or 4.
Use if input clock is above 14.4MHz
Controls division mode when DIVSEL is high. 0 = div
by 2, 1= div by 4.
Pager address bits to access programming of
K[21:0] and S
Pager data bits
PLL
[6:0]
DESCRIPTION
DESCRIPTION
DESCRIPTION
PP Rev 3.0 June 2006
Pre-Production
Analogue
Audio
Outputs,
Power-Up
Clock
Generation
Analogue
Audio
Outputs,
Power-Up
REFER TO
REFER TO
REFER TO
94
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