ISPLSI1032E70LTNI LATTICE [Lattice Semiconductor], ISPLSI1032E70LTNI Datasheet
ISPLSI1032E70LTNI
Related parts for ISPLSI1032E70LTNI
ISPLSI1032E70LTNI Summary of contents
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Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic ...
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Functional Block Diagram Figure 1. ispLSI 1032E Functional Block Diagram RESET Generic Logic Blocks (GLBs) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O ...
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Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
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External Timing Parameters 4 TEST 2 # PARAMETER COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max (Int.) ...
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External Timing Parameters 4 TEST 2 # PARAMETER COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max (Int.) ...
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Internal Timing Parameters 2 PARAM. # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t iosu 24 I/O Register Setup Time before Clock t 25 I/O Register Hold Time after Clock ioh t 26 I/O ...
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Internal Timing Parameters 2 PARAM. # DESCRIPTION Inputs t 22 I/O Register Bypass iobp t iolat 23 I/O Latch Delay t 24 I/O Register Setup Time before Clock iosu t 25 I/O Register Hold Time after Clock ioh t ioco ...
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Internal Timing Parameters PARAM. # Outputs t 49 Output Buffer Delay Output Buffer Delay, Slew Limited Adder sl t oen 51 I/O Cell OE to Output Enabled t 52 I/O Cell OE to Output Disabled odis t ...
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Internal Timing Parameters PARAM. # Outputs t 49 Output Buffer Delay Output Buffer Delay, Slew Limited Adder I/O Cell OE to Output Enabled oen t 52 I/O Cell OE to Output Disabled odis t ...
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Timing Model I/O Cell Ded. In #28 I/O Reg Bypass I/O Pin #22 (Input) Input GRP Loading Register Q D RST #29 #59 # Reset Distribution Y1,2,3 Y0 GOE 0 ...
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Maximum GRP Delay vs GLB Loads 6.0 5.0 4.0 3.0 2.0 1.0 Power Consumption Power consumption in the ispLSI 1032E device depends on two primary factors: the speed at which the device is operating, and the number of product terms ...
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Pin Description PLCC PIN NAME NUMBERS 26, 27, 28, 29, I I/O 3 30, 31, 32, 33, I I/O 7 35, 36, 37, I I/O 11 34, 38, 39, 40, 41, I ...
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Pin Configurations ispLSI 1032E 84-Pin PLCC Pinout Diagram VCC 21 ...
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Pin Configurations ispLSI 1032E 100-Pin TQFP Pinout Diagram ...
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Part Number Description ispLSI Device Family Device Number Speed f 125 = 125 MHz max f 100 = 100 MHz max MHz max MHz max MHz max ispLSI ...
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Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 125 125 100 ispLSI 100 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com. FAMILY fmax (MHz) tpd (ns) 70 ...