ISPLSI1032-60LG/883 LATTICE [Lattice Semiconductor], ISPLSI1032-60LG/883 Datasheet
ISPLSI1032-60LG/883
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ISPLSI1032-60LG/883 Summary of contents
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Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block ...
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Functional Block Diagram Figure 1. ispLSI and pLSI 1032 Functional Block Diagram RESET Generic Logic Blocks (GLBs) I/O 0 I/O 1 I I I I/O ...
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Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) Test Condition R1 A ...
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External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp 20 I/O Register Bypass t iolat 21 I/O Latch Delay t iosu 22 I/O Register Setup Time before Clock t ioh 23 I/O Register Hold Time after Clock t I/O ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs Output Buffer Delay t I/O Cell OE to Output Enabled oen 48 t odis 49 I/O Cell OE to Output Disabled Clocks t gy0 Clock Delay Global ...
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Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register D Q RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI and pLSI 1032 device depends on two primary factors: the speed at which the device is operating, and the number ...
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In-System Programmability The ispLSI devices are the in-system programmable versions of the Lattice Semiconductor High-Density pro- grammable Large Scale Integration (pLSI) devices. By integrating all the high voltage programming circuitry on- chip, programming can be accomplished by simply shifting data ...
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Shift Register Layout 159... Data In (SDI) 319... Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification. A logic "0" disables it. Specifications ispLSI and ...
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Pin Description Name PLCC Pin Numbers I I/O 3 26, 27, 28, I I/O 7 30, 31, 32, I I/O 11 34, 35, 36, I I/O 15 38, 39, 40, I/O 16 ...
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Pin Description Name TQFP Pin Numbers I I/O 3 17, 18, I I/O 7 21, 22, I I/O 11 29, 30, I I/O 15 33, 34, I I/O 19 40, ...
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Pin Description Name CPGA Pin Numbers I I/O 3 F1, H1, I I/O 7 K1, J2, I I/O 11 K3, L2, I I/O 15 L4, J5, I I/O 19 L7, ...
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Pin Configuration ispLSI and pLSI 1032 84-Pin PLCC Pinout Diagram I I ...
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Pin Configuration ispLSI and pLSI 1032 100-pin TQFP Pinout Diagram ...
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Pin Configuration ispLSI and pLSI 1032/883 84-Pin CPGA Pinout Diagram I/O38 I/O41 I/O42 I/O36 I/O39 I/O40 I/O35 I/O37 I/O33 I/O34 Y1 IN4 I/O32 Vcc I/O31 GND *SCLK IN3 I/O30 I/O29 I/O28 I/O26 I/O27 I/O25 I/O23 ...
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Part Number Description (is)pLSI Device Family Device Number Speed MHz max MHz max MHz max ispLSI and pLSI 1032 Ordering Information f Family ispLSI pLSI f Family ispLSI ...
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Copyright © 1997 Lattice Semiconductor Corporation CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ...