ISPLSI1032-60LG/883 LATTICE [Lattice Semiconductor], ISPLSI1032-60LG/883 Datasheet - Page 5

• Manufacturer Part Number: ISPLSI1032-60LG/883
• Description: High-Density Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
PARAMETER
External Timing Parameters
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
max (Int.)
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
en
dis
wh
wl
su5
h5
COND.
TEST
C
A
A
A
A
A
B
–
–
–
–
–
–
–
–
–
–
–
–
5
#
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
2
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
DESCRIPTION
Over Recommended Operating Conditions
1
Specifications ispLSI and pLSI 1032
4
5
3
(
tsu2 + tco1
1
)
MIN. MAX.
90.9
58.8
125
6.5
10
–
–
6
–
0
9
–
0
–
–
–
4
4
2
-90
12
17
10
15
15
15
–
–
–
–
8
–
–
–
–
–
–
–
–
MIN. MAX.
100
6.5
80
50
10
10
–
–
7
–
0
–
0
–
–
–
5
5
2
-80
15
20
10
12
17
18
18
–
–
–
–
–
–
–
–
–
–
–
–
1996 ISP Encyclopedia
MIN. MAX.
2.5
8.5
60
38
83
13
13
–
–
9
–
0
–
0
–
–
–
6
6
-60
Table 2-0030-32/90,80,60C
22.5
20
25
13
16
24
24
–
–
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns