LC4000C LATTICE [Lattice Semiconductor], LC4000C Datasheet - Page 43
![no-image](/images/no-image-200.jpg)
LC4000C
Manufacturer Part Number
LC4000C
Description
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.LC4000C.pdf
(91 pages)
- Current page: 43 of 91
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Power Supply and NC Connections
VCC
VCCO0
VCCO (Bank 0)
VCCO1
VCCO (Bank 0)
GND
GND (Bank 0)
GND (Bank 1)
NC
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
the bank shown.
ascending horizontally.
Signal
11, 33
6
28
12, 34
5
27
—
44-pin TQFP
2
12, 36
6
30
13, 37
5
29
—
48-pin TQFP
2
K2, A9
F3
E8
H3, C8
D3
G8
4032Z: A8, B10, E1,
E3, F8, F10, J1, K3
43
56-ball csBGA
ispMACH 4000V/B/C/Z Family Data Sheet
3
25, 40, 75, 90
13, 33, 95
45, 63, 83
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
100-pin TQFP
1
2
32, 51, 96, 115
3, 17, 30, 41, 122
58, 67, 81, 94, 105
1, 33, 65, 97
10, 24, 40, 113, 123
49, 59, 74, 88, 104
—
128-pin TQFP
2
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