ISPLSI2128E-135LT176 LATTICE [Lattice Semiconductor], ISPLSI2128E-135LT176 Datasheet

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ISPLSI2128E-135LT176

Manufacturer Part Number
ISPLSI2128E-135LT176
Description
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2128e_02
• SUPERFAST HIGH DENSITY IN-SYSTEM
• HIGH PERFORMANCE E
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
• OFFERS THE EASE OF USE AND FAST SYSTEM
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Features
PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 I/O Pins, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
— User-Selectable 3.3V or 5V I/O Supports Mixed-
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
Machines, Address Decoders, etc.
ispLSI 2128 Devices
f
t
(JTAG) Test Access Port
Voltage Systems
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 180 MHz Maximum Operating Frequency
pd = 5.0 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
Functional Block Diagram
Description
A0
A1
A2
A3
A4
A5
A6
A7
D7
B0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
SuperFAST™ High Density PLD
D6
B1
Global Routing Pool (GRP)
ispLSI
D5
B2
In-System Programmable
D4
B3
Logic
Array
Output Routing Pool (ORP)
D3
B4
Output Routing Pool (ORP)
D
D
D
D
D2
B5
Q
Q
Q
Q
®
D1
B6
2128E
GLB
November 1998
D0
B7
C7
C6
C5
C4
C3
C2
C1
C0
0139(9A)/2128

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ISPLSI2128E-135LT176 Summary of contents

Page 1

Features • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 I/O Pins, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2128E Functional Block Diagram RESET GOE 0 GOE 1 Megablock I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 ...

Page 3

Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...

Page 5

External Timing Parameters TEST 2 PARAMETER # 4 COND Data Prop Delay, 4PT Bypass, ORP Bypass pd1 Data Prop Delay pd2 Clk Freq with Internal Feedback max f – 4 Clk ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

Page 7

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE0 Derivations of su, h and co from the Product Term Clock Logic ...

Page 8

Power Consumption Power consumption in the ispLSI 2128E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax 500 450 400 ...

Page 9

Pin Description NAME TQFP PIN NUMBERS I I/O 4 27, 28, 31, 32, I I/O 9 35, 36, 37, 38, 41, 42, 43, 44, I I I/O 19 46, 47, ...

Page 10

Pin Configuration ispLSI 2128E 176-Pin TQFP Pinout Diagram 1 GND 2 I/O 114 3 I/O 115 4 I/O 116 5 I/O 117 6 I/O 118 I/O 119 7 I/O 120 8 9 I/O 121 10 VCCIO 11 GND 12 I/O ...

Page 11

Part Number Description ispLSI 2128E XXX X XXXX Device Family Device Number Speed f 180 = 180 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2128E Ordering Information FAMILY fmax (MHz) tpd (ns) ...

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