ISPLSI2192VE LATTICE [Lattice Semiconductor], ISPLSI2192VE Datasheet

ISPLSI2192VE

Manufacturer Part Number

ISPLSI2192VE

Description

Manufacturer

LATTICE [Lattice Semiconductor]

Datasheet

1.ISPLSI2192VE.pdf (15 pages)

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

• SuperFAST HIGH DENSITY IN-SYSTEM

• 3.3V LOW VOLTAGE ARCHITECTURE

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

• LEAD-FREE PACKAGE OPTIONS

2192ve_10

Features

PROGRAMMABLE LOGIC

— 8000 PLD Gates

— 96 I/O Pins, Nine or Twelve Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Pinout Compatible with ispLSI 2096V and 2096VE

— Interfaces with Standard 5V TTL Devices

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 3.3V In-System Programmability (ISP™) Using

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Machines, Address Decoders, etc.

Boundary Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

Market and Improved Product Quality

Interconnectivity

max = 225MHz Maximum Operating Frequency

pd = 4.0ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2192VE is a High Density Programmable

Logic Device containing 192 Registers, nine or twelve

Dedicated Input pins, three Dedicated Clock Input pins,

two dedicated Global OE input pins and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2192VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2192VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

The basic unit of logic on the ispLSI 2192VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 2192VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram

Description

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

SuperFAST™ High Density PLD

ispLSI

3.3V In-System Programmable

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Logic

Array

Output Routing Pool

2192VE

D Q

GLB

August 2004

0139/2192VE

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