ISPLSI5384VA-100LQ208 LATTICE [Lattice Semiconductor], ISPLSI5384VA-100LQ208 Datasheet
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ISPLSI5384VA-100LQ208
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ISPLSI5384VA-100LQ208 Summary of contents
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Features • SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 18,000 PLD Gates / 384 Macrocells — 288 I/O Pins — 384 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic ...
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Functional Block Diagram Figure 1. ispLSI 5384VA Functional Block Diagram (388 BGA Option) Input Bus Generic Logic Block VCCIO 1 I TOE I/O 1 I/O 2 I/O 3 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 ...
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Description (Continued) The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing maximum of 35 product terms for a single function. Alternatively, ...
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Figure 2. ispLSI 5384VA Block Diagram (288 I/O Version I 160 Global 5 160 Routing PT PT Pool 5 160 (GRP I/O CLK2 160 ...
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Figure 3. ispLSI 5000V Generic Logic Block (GLB) From Global Routing Pool ...
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Figure 4. ispLSI 5000V Macrocell PTOE GOE0 GOE1 TOE Shared PT Clock 0 Shared PT Clock 1 PT Clock CLK0 CLK1 CLK2 CLK3 PT Reset SET/RESET Shared PT (P)reset 0 PT Preset Shared PT (P)reset 1 Programmable Speed/Power Option Specifications ...
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Global Clock Distribution The ispLSI 5000V Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest ...
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Figure 6. Boundary Scan Register Circuit for I/O Pins SCANIN BSCAN (from previous Registers cell Shift DR Clock DR Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell) Shift DR Clock ...
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Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out SYMBOL PARAMETER t btcp TCK [BSCAN test] clock pulse width t btch TCK [BSCAN test] pulse width ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See figure 8) 3.3V TEST CONDITION R1 ...
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DC Electrical Characteristics for 2.5V Range SYMBOL PARAMETER V I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set ...
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External Switching Characteristics ...
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Internal Timing Parameters PARAM # DESCRIPTION I/O Buffer t idcom 22 Input Pad and Buffer, Combinatorial Input t idreg 23 Input Pad and Buffer, Registered Input t odcom 24 Output Pad and Buffer, Combinatorial Output t odreg 25 Output Pad ...
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Internal Timing Parameters PARAM # DESCRIPTION GRP t grpi 57 GRP Delay from I/O Pad t grpm 58 GRP Delay from Macrocell Global Control Delays t gclk01 59 Global Clock Delay t gclk23 60 Global Clock 2 ...
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Power Consumption Power consumption in the ispLSI 5384VA device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. ...
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Signal Descriptions Signal Name TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the ...
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PQFP Signal Locations Signal GOE0, GOE1 78, 79 TOE / I/O0 32 GSET/GRST 138 TCK 29 TDI 30 TDO 136 TMS 28 CLK0, CLK1 184,185 CLK2 / I/O89 162 CLK3 / I/O98 173 VCCIO 137 GND 3, 12, 19, ...
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Signal Locations Signal GOE0, GOE1 P9, P10 TOE / I/O0 K1 GSET/GRST H14 TCK K2 TDI K3 TDO G14 TMS J1 CLK0, CLK1 A7, B8 CLK2 / I/O89 B13 CLK3 / I/O98 A11 VCCIO H15 GND D10, D12, ...
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I/O Locations (Sorted by Ball) I/O # I/O # Ball Ball 124 A01 97 B11 115 A02 93 B12 114 A03 89* B13 113 A04 88 B14 110 A05 86 B15 109 A06 81 B16 105 A08 129 ...
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BGA Signal Locations Signal GOE0, GOE1 V11, U11 TOE / I GSET/GRST J18 TCK L4 TDI M1 TDO J20 TMS L3 CLK0, CLK1 C10, D10 CLK2 / I/O 119 A18 CLK3 / I/O 131 B13 VCCIO J19 ...
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BGA I/O Locations (Sorted by I/O) I/O # I/O # Ball Ball ...
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BGA I/O Locations (Sorted by Ball) I/O # I/O # Ball Ball 164 A02 121 B16 160 A03 116 B17 158 A04 169 C01 154 A05 166 C02 151 A06 162 C04 149 A07 156 C06 146 A08 152 ...
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BGA Signal Locations Signal GOE0, GOE1 AF14, AD13 TOE / I/O0 T1 GSET/GRST L25 TCK T2 TDI R3 TDO N24 TMS R1 CLK0, CLK1 A13, C14 CLK2 / I/O179 A23 CLK3 / I/O197 B17 VCCIO M26 GND A1, A2, ...
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BGA I/O Locations (Sorted by I/O) I/O # I/O # Ball Ball AC9 AF8 AD8 AE9 AF9 AE10 ...
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BGA I/O Locations (Sorted by Ball) I/O # I/O # Ball Ball 246 A03 243 C05 242 A04 239 C06 238 A05 236 C07 235 A06 232 C08 231 A07 225 C10 228 A08 221 C11 226 A09 217 ...
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Pin Configuration ispLSI 5384VA 208-pin PQFP (with Heat Spreader) I/O 124 1 I/O 125 2 3 GND I/O 126 4 I/O 127 5 I/O 128 6 7 VCC I/O 129 8 I/O 130 9 I/O 131 10 I/O 132 11 ...
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Part Number Description ispLSI 5384VA Device Family Device Number Speed f 125 = 125 MHz max f 100 = 100 MHz max MHz max Ordering Information ...