GAL20VP8B-15LP LATTICE [Lattice Semiconductor], GAL20VP8B-15LP Datasheet - Page 6

• Manufacturer Part Number: GAL20VP8B-15LP
• Description: High-Speed E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

In the Complex mode, macrocells are configured as output only or
I/O functions.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 14(17) & 22(26)) do not have input capability.
Designs requiring eight I/Os can be implemented in the Registered
mode.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Complex Mode
XOR
XOR
6
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
12(14) are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 15(18) through Pin 21(25) are configured to this
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 14(17) and Pin 22(26) are configured to this
function.
function.
Specifications GAL20VP8