A29L004UW-70 AMICC [AMIC Technology], A29L004UW-70 Datasheet - Page 7

• Manufacturer Part Number: A29L004UW-70
• Description: 512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

(s)TSOP packages)
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS
CMOS standby current (I
not within VSS
PRELIMINARY
RESET
: Hardware Reset Pin (N/A on 32-pin PLCC &
0.3V, the standby current will be greater.
(October, 2002, Version 0.0)
CC4
). If RESET is held at V
0.3V, the device draws
RP
, the device
IL
but
7
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/
operation is complete, which requires a time t
Embedded Algorithms). The system can thus monitor
RY/
complete. If RESET is asserted when a program or erase
operation is not executing (RY/
operation is completed within a time of t
Embedded Algorithms). The system can read data t
the RESET pin return to V
Refer to the AC Characteristics tables for RESET
parameters and diagram.
BY
BY
to determine whether the reset operation is
pin remains a “0” (busy) until the internal reset
AMIC Technology, Corp.
IH
.
A29L004 Series
BY
pin is “1”), the reset
READY
READY
(not during
RH
(during
after