ISP1130DL Philips Semiconductors, ISP1130DL Datasheet - Page 42

• Manufacturer Part Number: ISP1130DL
• Description: Universal Serial Bus compound hub with integrated keyboard controller
• Manufacturer: Philips Semiconductors

Table 67: TCON register: bit allocation
Philips Semiconductors
9397 750 06895
Objective specification
Bit
Symbol
Reset
Access
TF1
R
7
0
10.7 Watchdog timer
R/W
TR1
Table 68: TCON register: bit description
[1]
The Watchdog timer is a counter that resets the microcontroller upon overflow. This
allows recovery from erroneous processor states (e.g. caused by electrical noise or
RF-interference). To prevent the Watchdog timer from overflowing, the software must
reload the counter within a predefined (programmable) time.
The Watchdog timer is a 19-bit counter, consisting of an 11-bit prescaler and an 8-bit
SFR (WDT). The counter is clocked in state 2 of every CPU cycle (= 6 clocks) and
generates a reset when register WDT overflows. For a 12 MHz clock frequency, the
interval between overflows can be programmed between 1.024 ms (WDT = FFH) and
262.144 ms (WDT = 00H). After a reset the WDT register contains all zeroes.
To enable loading of the Watchdog timer, bit WLE in the PCON register must be set to
logic 1 (see
Watchdog timer can be disabled by writing 55H to the WDTKEY register, or by a
hardware reset.
Table 69: Watchdog timer registers: address mapping
Bit
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
Register
WDTKEY
WDT
6
0
[1]
All bits are individually addressable.
TF0
Table
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
R
5
0
51). When this is done for the first time, it also starts the timer. The
Rev. 01 — 23 March 2000
TR0
R/W
Description
Timer 1 overflow flag; set by hardware upon Timer 1 overflow;
cleared by hardware upon entering the interrupt service routine
Timer 1 run control bit; 0 = timer OFF, 1 = timer ON
Timer 0 overflow flag; set by hardware upon Timer 0 overflow;
cleared by hardware upon entering the interrupt service routine
Timer 0 run control bit; 0 = timer OFF, 1 = timer ON
external interrupt 1 flag; set by hardware when a keyboard
interrupt is detected; cleared by hardware upon entering the
interrupt service routine
triggering mode for external interrupt 1, set by software;
must always be logic 0 (= HIGH-to-LOW transition)
external interrupt 0 flag; set by hardware when a USB core
interrupt is detected; cleared by hardware upon entering the
interrupt service routine
triggering mode for external interrupt 0, set by software;
must always be 0 (= HIGH-to-LOW transition)
4
0
Access
write
write
USB compound hub with keyboard controller
IE1
R
3
0
R/W
IT1
2
0
Address (Hex)
FE
FF
© Philips Electronics N.V. 2000. All rights reserved.
IE0
R
1
0
ISP1130
R/W
IT0
0
0
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