ISP1130DL Philips Semiconductors, ISP1130DL Datasheet - Page 48

• Manufacturer Part Number: ISP1130DL
• Description: Universal Serial Bus compound hub with integrated keyboard controller
• Manufacturer: Philips Semiconductors

Table 76: I2C0CON register: bit allocation
Philips Semiconductors
9397 750 06895
Objective specification
Bit
Symbol
Reset
Access
CR2
R/W
7
0
11.3 Data transfer
ENS1
R/W
The I
EEPROM, e.g. upon a hardware or USB bus reset. The EEPROM must be enabled
and disabled using output pin MEMSEL/UPGL. To select the I
MX3/SCL and MX4/SDA, bit ENS1 in the I2C0CON register must be set to logic 1.
The number and the organization of the data bytes read from the EEPROM can be
determined by the firmware designer.
The I
Table 75: I
Table 77: I2C0CON register: bit description
Register
I2C0CON
I2C0STA
I2C0DAT
I2C0ADR
Bit
I2C0CON.7
I2C0CON.6
I2C0CON.5
I2C0CON.4
I2C0CON.3
6
0
[1]
2
2
C-bus interface can be used to read configuration data from an external
C-bus interface is accessed via a number of SFRs, shown in
2
C register addresses
R/W
STA
5
0
SFR address
D8H
D9H
DAH
DBH
Symbol
CR2
ENS1
STA
STO
SI
Rev. 01 — 23 March 2000
STO
R/W
4
0
Description
I
I
I
I
Description
selects I
Enable Serial I/O. A logic 1 enables the I
and sets pins MX3/SCL and MX4/SDA to logic 1. A logic 0
disables the I
allowing MX3/SCL and MX4/SDA to be used as open drain
I/O pins.
START flag. In Slave mode a logic 1 generates a START
condition as soon as the bus is free. In Master mode a
logic 1 generates a repeated START condition.
STOP flag. In maSter mode a logic 1 generates a STOP
condition. This bit is cleared by hardware if a STOP
condition is detected on the bus. In Slave mode a logic 1 can
be used to recover from an error: it causes SDA and SCL to
be released and the device to be unaddressed.
Serial Interrupt flag. A logic 1 signals a valid status change
(see
and the transfer to be suspended. This bit must be cleared
by software when servicing the interrupt.
2
2
2
2
C-bus control register
C-bus status register
C-bus data register
C-bus address register
Table
USB compound hub with keyboard controller
2
C-bus bit frequency in Master mode, see
R/W
83), causing the SCL LOW period to be stretched
SI
3
0
2
C-bus interface and clears bit STO to logic 0,
R/W
AA
2
0
© Philips Electronics N.V. 2000. All rights reserved.
2
C-bus function of pins
CR1
R/W
1
0
Table
2
ISP1130
C-bus interface
75.
Table 78
CR0
R/W
0
0
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