Z87L01 Zilog., Z87L01 Datasheet
Z87L01
Related parts for Z87L01
Z87L01 Summary of contents
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... External Program Memory Accessible by the DSP Core Bus Interface to Z87010 ADPCM Processor Static CMOS for Low Power Consumption 3.0V to 3.6V, - +70 C, Z87L01 4.5V to 5.5V, - +70 C, Z87001 16.384 MHz Base Clock The Z87001 supports a specific cordless phone system design that uses frequency hopping and digital modulation to provide extended range, high voice quality, and low sys- tem costs ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller GENERAL DESCRIPTION (Continued) plexing of the 32 kbps voice data and 4 kbps command data between handset and base station. The Z87001 pro- vides thirty-two I/O pins, including four wake-up inputs and two CPU interrupt inputs. These programmable I/O pins al- low a variety of user-determined phone features and board layout configurations ...
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... Rate Buffer 256 Word RAM 0 Frame Counter(s), Event Trigger, DSP Core T/R Switch Ctrl, Power On/Off Ctrl, Antenna Select Figure 2. Z87001 Functional Block Diagram Z87001/Z87L01 VXDATA[7..0] VXADD[2..0] Z87010 VXSTRB Interface VXRWB VXRDYB CLKOUT CODCLK 256 Word Port 0 P0[15 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller PIN DESCRIPTION TX 1 AGND RX AVDD VREF RFEON addr12 P115 addr11 GND addr10 P114 addr9 P113 addr8 P112 addr7 VDD addr6 P111 addr5 P110 addr4 P19 addr3 GND addr2 P18 addr1 P17 addr0 P16 idata15 ...
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... External register address bus ADPCM processor read/write control trice ROMless mode select ADPCM processor address bus Clock to codec (2.048 MHz) irwb External register read/write control Master reset Interrupt enable Z87001/Z87L01 Direction 1 Output – Input – – Output Output Input/Output – ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller PIN DESCRIPTION (Continued) No Symbol 129 130 MCLK 132 triadd 133 PAON 134 dspclk 135 SYLE 137 RXSW 139 TXSW 142 PWLV 143 RSSI 6 Table 1. 144 Pin QFP Pin Configuration Function halt Halt/ single step control Master clock (16 ...
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... STANDARD TEST CONDITIONS The electrical characteristics listed below apply for the fol- lowing standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pins. Standard test conditions are as follows: 3.0V < V < 3.6V (Z87L01) DD 4.5V < V < 5.5V (Z87001) DD GND = 0V T ...
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... Output Low Current, ICE pins (1)) OLICE T Operating Temperature A Notes: 1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. Maximum 3 pins total from P0[15..0] and P1[15..0] 8 Table 3. 5V 0.5V Operation (Z87001) Parameter Table 4. 3.3V 0.3V Operation (Z87L01) Parameter 0.7 V GND -0 Min Max 4.5 5.5 2 0.3 DD GND -0 ...
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... Test Condition V min, I max DD OH min, I max DD OHICE V min, I max DD OL1 V min, I max DD OL2 min, I max DD OLICE Table 6. 3.3V 0.3V Operation (Z87L01) Test Condition V min, I max DD OH min, I max DD OHICE V min, I max DD OL1 V min, I max DD OL2 min, I max DD OLICE ...
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... Acquisition time Settling time Conversion time Aperture delay Aperture uncertainty(2) Input voltage range (p-p) Reference voltage Z87L01 Z87001 Input resistance Input capacitance Notes: Window of time while input signal is applied to sampling capacitor; see next figure. Uncertainty in sampling time due to random variations such as thermal noise. ...
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... Acquisition Settling Time Time Figure 6. 1-Bit ADC Definition of Terms Minimum Typical - 3.0 3.3 4.5 5.0 0- Z87001/Z87L01 Latched Output Conversion + Time (for digital output) Maximum Units - bit 1 LSB 0.5 LSB 70 mW 120 ns 2 Msps 3 Kohm - ...
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... Power dissipation load Power dissipation load, Stop mode Conversion time (input change to output change) Rise time (full swing) Output slew rate Output voltage range Supply Range (= Z87L01 Z87001 Output load resistance Output load capacitance 12 Table 9. 4-bit DAC (Temperature: -20/+70 C) Minimum - - ...
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... ROMless Spread Spectrum Cordless Phone Controller , AV , GND, AGND, The RX analog input pin has an input capacitance pF. The RSSI analog input pin has an input capacitance of 10 pF. Table 10. Clocks, Reset and RF Interface Parameter Z87001/Z87L01 Min Max Units ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller ADPCM Processor Interface The Z87001 is a peripheral device for the ADPCM Proces- sor. The interface from the Z87001 perspective is com- posed of an input address bus, a bidirectional data bus, strobe and read/write input control signals and a ready/wait output control signal ...
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... CLKOUT CODCLK MCLK RESETB PAON TXSW RXSW RFEON SYLE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TwC(2) TrC(3) TfC(3) TpC (1) TfCC(4) TrCC(4) TfCO(5) TrCO( TwR(6) TfRF(7) TrRF(7) Figure 7. Transceiver Output Signal Z87001/Z87L01 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller VXADD VXRWB VXSTRB VXDATA VXRDYB VXADD VXRWB VXSTRB VXDATA VXRDYB 16 TsAS(8) TaDrS(10) VXDATA Read Cycle TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle Figure 8. Read/Write Cycle TImings Zilog ThSA(9) ThDrS(11) ThSA(9) ...
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... Figure 9. Read/Write Cycle Timing with Wait StatE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TsAS(8) TaDrRY(15) VXDATA Read Cycle with Wait State TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle with Wait State Z87001/Z87L01 ThSA(9) ThDrS(11) TdSRY(16) ThSA(9) ThDwS(14) TdSRY(16 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller PIN FUNCTIONS V Digital power supply. DD. GND. Digital ground Analog power supply. DD AGND. Analog ground. V (analog reference). This signal is the reference volt- REF age used by the high speed analog comparator to sample the RX input signal. RX (analog input). This is the RX IF receive signal from the RF module, input to the analog comparator and FSK demodulator ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller FUNCTIONAL DESCRIPTION The functional partitioning of the Z87001 is shown in Fig- ure 2. The chip consists of a receiver, a transmitter, and several additional functional blocks.The receiver consists of the following blocks: Receive 1-bit ADC Demodulator, including: – IF Downconverter – ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Receive 1-Bit ADC The incoming receive signal at the RX analog input pin is sampled by a 1-bit analog-to-digital converter at 8.192 MHz. The receive signal is FSK-modulated (Frequency Shift Keying) with a carrier frequency of 10.7 MHz (Intermediate Frequency, or IF). The instantaneous frequency varies be- tween 10 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller FUNCTIONAL DESCRIPTION (Continued) synchronizer, based on detection of a “unique word” fol- lowing the preamble. The receiver also features a signal-to-noise ratio detector, which allows the DSP software to detect noisy channels and eliminate them from the frequency hopping cycle. The ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Tx signal Transmit 4-Bit DAC The transmit DAC clocks one new NCO value out of the Z87001 every 8.192 MHz period. Only the 10.7 MHz alias frequency component of the transmit signal (2.508 + 8.192 MHz image) is filtered, amplified and upconverted to the 900 MHz ISM band by the companion RF module ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller FUNCTIONAL DESCRIPTION (Continued) The DSP core is characterized by an efficient hardware ar- chitecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply-accumu- late of two 16-bit operands. Most instructions are executed in one clock cycle. The DSP core is operated at the internal speed of 8.192 MHz ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION Automatic Frequency Control Loop (Receiver) and Modulator AFC Loop The AFC loop consists of a bias estimator block, which de- termines frequency offsets in the incoming signal, an adder, to add this bias to the 460 kHz frequency control word driving the NCO, and various interface points to the DSP core processor ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) Modulator Control The MOD_FREQ fields specify the carrier center frequen- cy (should be programmed to 2.508 MHz) and deviation for the FSK signal (should be programmed to 32.58 kHz). In addition, wave shaping is performed on bit transitions, in order to satisfy FCC regulations four different inter- mediate deviation values are programmable for each of the two FSK states ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller The loop filter is controlled by the DSP core processor. The DSP core can implement a first order loop by setting the SECOND_ORDER field to zero. BSYNC_GAIN would then be set to “divide-by-1” operation to provide a wide closed loop bandwidth and thus a quick acquisition of the bit clock ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) Handset FRAME_COUNTER 0 1 SYLE timing Receive data at RX pin Figure 7. Frame Counter and UW_LOCATION on Handset Two modes of search are programmable through the SYNC_SEARCH_MODE field: “full search” and “window search”. The full search is used by the handset when first acquiring the signal from the base station ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller The following table summarizes the fields allowing control of frame synchronization and basic frame timing. Table 3. Frame Synchronizer Control Fields Field Register SYNC_SEARCH-MODE SSPSTATE SYNC_SEARCH_WORD SSPSTATE UW_LOCATION RX_CONTROL WINDOW_SIZE CONFIG1 MULTIPLEX_SWITCH SSPSTATE SYNC_ACQ_IND SSPSTATUS SYNC_ACQ_CLEAR ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) The following figure and table summarize the RF interface control fields. HBSW DSP Core Processor TX_ENABLE Table 4. Timing and RF Interface Control Fields Field RFEON_POLARITY HOP_ENABLE SYLE_POLARITY TX_ENABLE MOD_PWR_ON RFRX_PWR_ON/OFF DEMOD_PWR_ON/OFF RFRX_POLARITY RFTX_PWR_ON/OFF RFTX_POLARITY ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Sleep Mode To save the phone’s battery life on the handset, the Z87001 can be operated in sleep mode while the phone is not in use. The sleep mode is entered by software com- mand. The sleep mode first needs to be enabled by setting the SLEEP_WAKE field ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) The operation of the receive rate buffer is identical. The Z87001 core processor must set the nibble address in RX_BUF_ADDR, then read RX_BUF_DATA. If the RX_AUTO_INCREMENT bit is set, the read address is automatically incriminated (modulo 36 = number of nibbles in rate buffer) after each data read. ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Table 7. Data and Control Access to Rate Buffers Field RX_AUTO_INCREMENT RX_BUF_ADDR TX_AUTO_INCREMENT TX_BUF_ADDR RX_BUF_DATA TX_BUF_DATA TX_BUF_DATA RX_BUF_VP_ADDR TX_BUF_VP_ADDR TX_RX_NIBBLE_MARKER ADDITIONAL FEATURES Power Control The Z87001 features several means of measuring and controlling power levels. One input pin (RSSI) connects an external “ ...
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... SNR estimate FCW value 8-bit ADC data (RSSI) Re Rate Buffer data Bit Sync monitoring INT, WAKEUP pin control, 4-bit DAC data (PWLV) Bit Sync monitoring Z87001/Z87L01 WRITE DESCRIPTION TABLE # Table 25 size, Bias Threshold Table 27 Table 28 Table 29 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) The bank is selectable in software by writing to the core’s status register (see Table 24). Once a bank is selected, Bank Status Register Bank 0 xxxx xxxx x00x xxxx b Bank 1 xxxx xxxx x01x xxxx b Bank 2 xxxx xxxx x10x xxxx b ...
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... Returns value of sleep counter when sleep mode is interrupted by a “wake” signal R 00h Normal expiration of sleep counter 01h One frame left before normal expiration ••• FFh 255 frames left before normal expiration Z87001/Z87L01 Description 35 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) SSPSTATE Bank 3 Field Bit Position SW_SYLE f--------------- STOP_CODCLK -e-------------- DBP_STOP_CLOCK --d------------- BSYNC_GAIN ---c------------ BIAS_ENABLE ----b----------- TX_ENABLE -----a---------- SYNC_SEARCH_WORD ------9--------- SYNC_SEARCH_MODE -------87------- HOP_ENABLE ---------6------ SYNC_ACQ_CLEAR ----------5----- FRAME_START_CLEAR -----------4---- SLEEP_WAKE ------------3--- MULTIPLEX_SWITCH -------------21- 36 Table 14. Bank 3 Register Description EXT2 R/W Data Description Controls accelerated synthesizer programming after sleep ...
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... STMUX (bit inv. enabled; ADPCM Proc. access disabled) 10 Reserved 11 TMUX (bit inversion and ADPCM Processor access enabled) Command bit to place the Z87001 in sleep mode R Returns last value written W 0->1 A transition from causes Z87001 sleep mode Z87001/Z87L01 1 37 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) SSPSTATUS Bank 3 Field Bit Position FRAME_COUNTER fedcba987------ RESERVED ---------65---- HAND_BASE_SEL -----------4--- SYNC_ACQ_IND ------------3-- FRAME_START_IND ------------2-- RESERVED -------------10 Notes: FRAME_COUNTER. Read the double-buffered current value of the Frame Counter. On the handset, a single frame counter is used to clock transmit and receive events. ...
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... Table 18. Bank 3 Register Description EXT6 R/W Data Independent control of Port 1 pin direction R/W ..0. Pin in input mode ..1. Pin in output mode Table 19. Bank 3 Register Description EXT7 R/W Data Access to Port 1 data R XXXXh Reads pin values W XXXXh Writes output pin values Z87001/Z87L01 Description Description Description 39 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Bank 2 Registers VP_INOUT Bank 2 Field Bit Position RESERVED fedcba98-------- VP_STATUS --------76543210 VP_COMMAND --------76543210 RX_CONTROL Bank 2 Field Bit Position SNR_ESTIMATE fedcba9876543210 UW_LOCATION -------876543210 Notes: SNR_ESTIMATE. This value is updated every frame. It should be read by the software during the frequency hopping guard time of the next frame. ...
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... Updates bias value Table 25. Bank 2 Register Description EXT5 R/W Data R Returns effect Determines modulator turn-on time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Z87001/Z87L01 Description Description Description 41 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) DEMOD_PWR_CTRL Bank 2 Field Bit Position RFEON_POLARITY f--------------- DEMOD_PWR_ON -edcba98-------- RESERVED --------7------- DEMOD_PWR_OFF ---------6543210 Notes: 1. DEMOD_PWR_ON, DEMOD_PWR_OFF. Controls internal receive hardware and the RXSW output pin. The turn-on and off times are given in number of received bit periods and are referenced to the Receive Frame Counter. Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For DEMOD_PWR_ON, the two bits are “ ...
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... R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Determine PAON output pin turn-off time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-off time (=(x modulo 128) - Z87001/Z87L01 Description 43 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Bank 1 Registers RATE_BUF_ADDR Bank 1 Field Bit Position RESERVED f-------------- RX_AUTO_INCREMENT -e------------- RX_BUF_ADDR --dcba98-------- RESERVED --------7------- TX_AUTO_INCREMENT ---------6------ TX_BUF_ADDR ----------543210 44 Table 28. Bank 1 Register Description EXT0 R/W Data R Returns effect Controls the auto-increment feature of the Rx rate R buffer W 0 Returns 0 1 Disables auto-increment ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) RATE_BUF_DATA Bank 1 Field Bit Position RX_BUF_DATA ------------3210 TX_BUF_DATA ------------3210 TX_BUF_VP_ADDR --dcba98-------- RX_BUF_VP_ADDR ----------543210 TX_RX_NIBBLE_MARKER fedcba9876543210 MOD_FREQ fedcba9876543210 Note: The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller RESERVED Bank 1 Field Bit Position RESERVED fedcba9876543210 CONTROL Bank 1 Field Bit Position RESERVED fedcb----------- FS_INT_ENABLE -----a---------- INTERRUPT_0_ENABLE ------9--------- INTERRUPT_2_ENABLE -------8-------- P0_WAKEUP_ENABLE --------7654---- TX_PWR_DAC_DATA ------------3210 Note: P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87001 sleep mode. ...
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... Table 35. Bank 0 Register Description EXT6 R/W Data R Returns effect Read access to the integrated symbol error from the bit synchronizer’s second order loop R XXh Reads error data bits [7..0] (bits [23..8] are in bank1, EXT2 effect Z87001/Z87L01 Description Description 47 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller RFRX_PWR_CTRL Bank 0 Field Bit Position RFRX_POLARITY f--------------- RFRX_PWR_ON -edcba98-------- RESERVED --------7------- RFRX_PWR_OFF ---------6543210 Notes: 1. RFRX_POLARITY. Caution: notice the inverse polarity of the TXSW pin. 2. RFRX_PWR_ON, RFRX_PWR_OFF. Controls the TXSW output pin. The turn-on and off times are given in number of trans- mitted bit periods and are referenced to the TRANSMIT (!) Frame Counter ...
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... CIEF None COPF None CP<src1>,<src2> A,<pregs> A,<dregs> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<limm> DEC [<cc>,]<dest> <cc>A, A INC [<cc>,] <dest> <cc>, [<cc>,]<address> <cc>,<direct> <direct> Z87001/Z87L01 # # Words Cycles Example 1 1 ABS NC ABS ADD A,P0 ADD A,D0 ADD A,#%1234 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Instruction Description Opcode LD Load destination with source 0000000 0000001 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000 MLD Multiply 1010010 1010010 1011011 1011011 MPYA Multiply and add ...
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... None SRA<cc>,A <cc>,A A SUB<dest>,<src> A,<pregs> A,<dregs> A,<limm> A, <memind> A, <direct> A, <regind> A, <hwregs> XOR <dest>,<src> A, <pregs> A, <dregs> A, <limm> A, <memind> A, <direct> A, <regind> A, <hwregs> Z87001/Z87L01 # # Words Cycles Example 1 1 POP P0 POP D0 POP @P0 POP PUSH P0:0 ...