HMP8117CN Intersil Corporation, HMP8117CN Datasheet - Page 23

• Manufacturer Part Number: HMP8117CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: Intersil Corporation

Sub-Addresses: 40
Sub-Addresses: 07
ADDRESS
NUMBER
NUMBER
20
24
31
34
SUB-
1B
1C
1D
1E
BIT
1F
32
35
36
37
41
42
50
51
52
53
7F
6-5
2-1
H
H
H
H
BIT
7-0
7
4
3
-23
-29
/30
/33
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Reserved
Video Timing
Standard
Auto Detect
Video Standard
Setup Select
Reserved
Saturation
Color Gain Adjust
Video Gain Adjust
Sharpness
Host Control
Closed Caption Data Registers
WSS Data & CRC Registers
Start H_BLANK MSB/LSB
End H_BLANK
Start V_BLANK MSB/LSB
End V_BLANK
End HSYNC
HSYNC Detect Window
MV Control
Reserved
Programmable Fractional Gain
MV Stripe Gate
Reserved
AGC Hysteresis
Device Revision
Product ID
FUNCTION
H
H
FUNCTION
, 43
, 09
CONTROL REGISTER
H
H
-4F
, 0D
H
H
are reserved. Reads from these registers may return non-zero values.
23
, 2A
H
These bits are read only unless bit 4 = “0”.
00 = (M) NTSC
01 = (B, D, G, H, I, N) PAL
10 = (M) PAL
11 = Combination (N) PAL; also called (N
0 = Manual selection of video timing standard
1 = Auto detect of video timing standard
Typically, this bit should be a “1” during (M) NTSC and (M, N) PAL operation. Otherwise, it should
be a “0”.
0 = Video source has a 0 IRE blanking pedestal
1 = Video source has a 7.5 IRE blanking pedestal
-2F
This 8-bit register specifies the last two digits of the product number. Data written to this read-
only register is ignored.
H
TABLE 10. CONTROL REGISTER SUMMARY (Continued)
, 38
H
-3F
H
TABLE 12. INPUT FORMAT REGISTER.
and 54
TABLE 11. PRODUCT ID REGISTER
DEFAULT
03
01
RESET/
VALUE
H
SUB ADDRESS = 00
SUB ADDRESS = 01
7A
0C
-7E
80
40
80
10
00
80
00
H
12
30
20
26
00
14
02
00
01
H
/4A
/02
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
HMP8117
H
H
H
are unused. Reads from these registers return 00
VALUE
Table 3
Table 3
Table 3
Table 3
Table 3
USE
F0
DESCRIPTION
90
30
21
22
DESCRIPTION
C
H
H
H
H
H
) PAL
H
H
Set bit 7 for Soft Reset. Set bit 6 for Power Down.
BLANK programming changes for each video standard.
(same as above)
(same as above)
(same as above)
(same as above)
A wider window tolerates poorly timed video sources.
Set bits 5-4 to 11
A slower PFG improves AGC stability.
Set bit 5 to “1” for optimum performance.
Larger hysteresis improves AGC stability.
Production baseline revision is 01
B
for optimum performance.
COMMENTS
H
. Writes are ignored.
H
.
RESET
STATE
RESET
STATE
17
00
00
0
1
1
B
B
B
H
B
B