SAF-C502-2R20N Siemens Semiconductor Group, SAF-C502-2R20N Datasheet - Page 29

Manufacturer Part Number

SAF-C502-2R20N

Description

8-Bit CMOS Microcontroller

Manufacturer

Siemens Semiconductor Group

Datasheet

1.SAF-C502-2R20N.pdf (46 pages)

– Starting and refreshing the WDT

Table 13

Starting and Refreshing the WDT

Function

Starting WD

Refreshing WD

– Watchdog reset and watchdog status flag (WDTS)

Semiconductor Group

Table 13 gives an overview how to start and refresh the WDT. The mentioned bits are located in

SFR WDCON.

If the software fails to clear the watchdog in time, an internally generated watchdog reset is

entered at the counter state 7FFC H . The duration of the reset signal then depends on the

prescaler selection (either 8 or 128 cycles). This internal reset differs from an external one in so

far as the Watchdog Timer is not disabled and bit WDTS (SFR WDCON) is set. The WDTS is a

flip-flop, which is set by a Watchdog Timer reset and can be cleared by an external hardware

reset. Bit WDTS allows the software to examine from which source the reset was activated. The

bit WDTS can also be cleared by software.

SETB

Example

SWDT

WDT

SWDT

Remarks

Cannot be stopped during active mode of the

device. WDT is halted during idle mode, power

down mode or the oscillator watchdog reset is

active.

Double instruction sequence

(setting bit WDT and SWDT consecutively) to

increase system security.

C502