SAF-C505-2RM Siemens Semiconductor Group, SAF-C505-2RM Datasheet - Page 57
SAF-C505-2RM
Manufacturer Part Number
SAF-C505-2RM
Description
8-Bit CMOS Microcontroller
Manufacturer
Siemens Semiconductor Group
Datasheet
1.SAF-C505-2RM.pdf
(85 pages)
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Table 13
Access Modes Selection
Access Mode
Program OTP memory byte
Read OTP memory byte
Program OTP lock bits
Read OTP lock bits
Read OTP version byte
Lock Bits Programming / Read
The C505A/C505CA has two programmable lock bits which, when programmed according table 14,
provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can
also be read.
Table 14
Lock Bit Protection Types
Lock Bits at D1,D0
Semiconductor Group
D1
1
1
0
0
D0
1
0
1
0
Protection
Level
Level 0
Level 1
Level 2
Level 3
EA/
V
V
V
V
V
V
PP
PP
PP
IH
IH
IH
Protection Type
The OTP lock feature is disabled. During normal operation of
the C505A/C505CA, the state of the EA pin is not latched on
reset.
During normal operation of the C505A/C505CA, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the ROM/OTP verification mode 2 for
protection level 1. Further programming of the OTP memory is
disabled (reprogramming security).
Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.
Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C505A/C505CA
is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.
PROG
H
H
H
57
PRD
H
H
1
H
H
L
PMSEL
0
H
L
H
Byte addr.
of version
Address
(Port 2)
A8-14
A0-7
byte
C505A / C505CA
–
C505 / C505C
D1,D0 see
1997-12-01
table 14
(Port 0)
Data
D0-7
D0-7
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