SAF-C505-2RM Siemens Semiconductor Group, SAF-C505-2RM Datasheet - Page 65
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SAF-C505-2RM
Manufacturer Part Number
SAF-C505-2RM
Description
8-Bit CMOS Microcontroller
Manufacturer
Siemens Semiconductor Group
Datasheet
1.SAF-C505-2RM.pdf
(85 pages)
- Current page: 65 of 85
- Download datasheet (336Kb)
Notes:
1)
2) During the sample time the input capacitance
3) This parameter includes the sample time
4) T
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group
V
these cases will be 00
internal resistance of the analog source must allow the capacitance to reach their final voltage level within
After the end of the sample time
result.
conversion clock
guaranteed by design characterization for all other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
UE
AIN
(max.) is tested at – 40
may exeed
t
V
ADC
AGND
H
depend on programming and can be taken from the table on the previous page.
or FF
or
V
H
AREF
, respectively.
T
t
A
S
, changes of the analog input voltage have no effect on the conversion
up to the absolute maximum ratings. However, the conversion result in
125 C;
t
S
C
, the time for determining the digital result. Values for the
V
AIN
CC
65
must be charged/discharged by the external source. The
5.5 V;
V
AREF
V
CC
+ 0.1 V and
C505A / C505CA
C505 / C505C
V
SS
1997-12-01
V
AGND
. It is
t
S
.
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