HD6433935 Hitachi, HD6433935 Datasheet - Page 124

• Manufacturer Part Number: HD6433935
• Description: 8-Bit MICROCONTROLLER
• Manufacturer: Hitachi

5.7
5.7.1
If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2
is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed)
mode results from IRQ
timer G, IRQ
transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
The CPU may operate at a 1/2 state faster timing at transition to active (medium-speed) mode.
5.7.2
Active (medium-speed) mode is cleared by a SLEEP instruction.
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit
in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is
cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3
in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See 5.8, Direct Transfer, below for details.
When the RES pin is driven low, a transition is made to the reset state and active (medium-speed)
mode is cleared.
5.7.3
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
112
Clearing by SLEEP instruction
Clearing by RES pin
Active (Medium-Speed) Mode
Transition to Active (Medium-Speed) Mode
Clearing Active (Medium-Speed) Mode
Operating Frequency in Active (Medium-Speed) Mode
0
or WKP
7
0
, IRQ
to WKP
1
or WKP
0
interrupts in watch mode, or any interrupt in sleep mode. A
7
to WKP
0
interrupts in standby mode, timer A, timer F,