HD6433935 Hitachi, HD6433935 Datasheet - Page 395

• Manufacturer Part Number: HD6433935
• Description: 8-Bit MICROCONTROLLER
• Manufacturer: Hitachi

The following describes the sequence of events between the Host and the FLEX decoder required
to handle a temporary address:
Following an Address Packet, the host will receive a Vector Packet with V
i
to this pager). The system may send either and i
assigning a temporary address. The vector packet with and i
temporary address is assigned and the frame in which the temporary address is expected. The
vector packet with and i
of the expected frame (essentially indicating 64 frames in which to look for the temporary
address), and a message sequence number. When the vector packet with and i
received on a long address, the specific assign frame is included in the mes-sage word sent
after the vector.
The FLEX decoder will increment the corresponding temporary address counter for each
temporary address assignment vector received and begin to decode all of the follow-ing
frames. Note that this implies a single dynamic group assignment that is implemented by
sending two short instructions (one for each temporary address assignment mode of the short
instruction vector) will cause the corresponding temporary address counter to incre-ment
twice.
The FLEX decoder continues to decode all of the frames and passes any address infor-mation,
vector information and message information to the host followed by a status packet indicating
the end of each frame and the current frame number.
There are several scenarios which may occur with temporary addresses.
1
i
0
1. The temporary address is not found in the any of the assigned frames and therefore the
2. The temporary address is found in the frame it was assigned and was not a fragmented
3. The temporary address is found in the assigned frame and it is a fragmented message.
= 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned
host must terminate the temporary address mode by sending an All Frame Mode Packet
to the FLEX decoder with the “DTA” bit of the particular temporary address set (if both
temporary address assignment packets were used to assign the temporary address, the
“DTA” bit must be set twice to disable the temporary address).
message. Again, the host must terminate the temporary address mode by sending an All
Frame Mode Packet to the FLEX decoder with the “DTA” bit of the particular
temporary address set (if both temporary address assignment packets were used to
assign the temporary address, the “DTA” bit must be set twice to disable the temporary
address).
In this case, the host must follow the rules for Operation of a Fragmented Message and
determine the proper time to stop the all frame mode operation. In this case, the host
must write to the “DAF” bit with a “1” and the appropriate “DTA” bit with a “1” in the
All Frame Mode Register in order to terminate both the fragmented message and the
temporary address (if both temporary address assignment packets were used to assign
the temporary address, the “DTA” bit must be set twice to disable the temporary
address).
2
i
1
i
0
= 010 will indicate which temporary address is assigned, the MSb
2
i
1
i
0
= 000 or and i
2
i
1
i
0
= 000 will indicate which
2
i
1
i
0
= 010 or both when
2
V
2
1
i
V
1
i
0
0
= 001 and i
= 010 is
383
2