CS8427 Cirrus Logic, CS8427 Datasheet
CS8427
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CS8427 Summary of contents
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... FAX: (512) 445 7581 http://www.cirrus.com General Description The CS8427 is a stereo digital audio transceiver with AES3 and serial digital audio inputs, AES3 and serial digital audio outputs, along with comprehensive control ability through a 4-wire microcontroller port. Channel sta- tus and user data are assembled in block sized buffers, making read/modify/write cycles easy ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS8427 DS477PP3 ...
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... User Data Buffer Control (13h) ..................................................................................... 38 12.18 Q-Channel Subcode Bytes (14h - 1Dh) (Read Only) ......................................... 38 12.19 OMCK/RMCK Ratio (1Eh) (Read Only)........................................................................ 39 12.20 C-bit or U-bit Data Buffer (20h - 37h) ........................................................................... 39 12.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ................................................. 39 13. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 40 14. HARDWARE MODE DESCRIPTION ................................................................................... 42 14.1 Serial Audio Port Formats ............................................................................................. 42 15 ...
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... Figure 3. SPI Mode timing............................................................................................................... 8 Figure 4. Two-Wire Mode timing ..................................................................................................... 9 Figure 5. Recommended Connection Diagram for Software Mode............................................... 10 Figure 6. CS8427 Internal Block Diagram..................................................................................... 12 Figure 7. Jitter Attenuation Char.’s of PLL with kHz Fs Filter Components-AES3 ............ 18 Figure 8. Jitter Attenuation Char.’s of PLL with kHz Fs Filter Components-AES3 .......... 18 Figure 9 ...
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... Supply Current at 96 kHz frame rate Supply Current in power down Ambient Operating Temperature:CS8427-CS & -CZ Notes: 1. ‘-CS’ and ‘CZ’ parts are specified to operate over -10 ° °C but are tested at 25 °C only. 2. ‘- IS’ and ‘-IZ’ parts are tested over the full -40 ° °C temperature range. ...
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... Notes: 5. PLL is bypassed (Bit RXD0 in Clock Source Control register set to 1), clock is input to the RMCK pin - °C for ‘IS’ & ‘IZ’ V±10%, VL+ = 3/5 V ±5/10%, Inputs pF) Symbol (Note 5) (Note 5) CS8427 Min Typ Max Units µs 200 - - 4 ...
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... Figure 2. Audio Port Slave Mode and Data Input Timing Min Typ Max dpd smd lmd - sckw sckl sckh lrckd lrcks lrckd lrcks sckh sckl t sckw CS8427 Units dpd 7 ...
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... Figure 3. SPI Mode timing Min Typ Max 6.0 sck t 1 csh css scl sch dsu 100 100 f2 t csh CS8427 Units MHz µ DS477PP3 ...
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... Figure 4. Two-Wire Mode timing Min Typ Max 100 scl t 4 buf t 4 hdst t 4 low t 4 high t 4 sust hdd t 250 - - sud 4 susp Repeated Stop Start hdst t sust t r CS8427 Units kHz µs µs µs µs µs µ µs t susp 9 ...
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... OLRCK ISCLK OSCLK SDIN SDOUT RMCK SDA/CDOUT OMCK AD0/CS SCL/CCLK AD1/CDIN INT EMPH / RERR RST TCBL H/S AGND FILT DGND RFILT CFILT CRIP CS8427 + Digital Supply AES3/ Cable SPDIF Interface Equipment 3-wire Serial Audio Input Device Microcontroller DS477PP3 ...
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... GENERAL DESCRIPTION The CS8427 is an AES3 transceiver intended to be used in digital audio systems. Such systems include digital mixing consoles, effects processors, digital recorders and computer multimedia systems. 3.1 Audio Input/Output Ports The CS8427 has the following Audio ports: • Serial Audio Input Port • ...
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... E buffers into the F buff- ers. In applications using AES3 in and AES3 out, the CS8427 can automatically transceive user data that conforms to the IEC60958 format. The CS8427 also gives the user access to the bits necessary to comply with the serial copy management system (SCMS) ...
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... The Clock Source Control Register bits determine which clock is used to operate the CS8427. The CS8427 has another constraint related to the state machine that governs the startup of the part. The startup state machine doesn’t complete its pro- ...
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... Figure 17 shows a selection of common input for- mats, along with the control bit settings. The clock- ing of the input section of the CS8427 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL operation is de- scribed in “AES3 Receiver” on page of use with the serial audio input port, the PLL locks onto the leading edges of the ILRCK clock ...
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... External components are used to terminate and iso- late the incoming data cables from the CS8427. These components are detailed in External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on page DS477PP3 6 ...
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... Error Reporting and Hold Function While decoding the incoming AES3 data stream, the CS8427 can identify several kinds of error, in- dicated in the Receiver Error register. The UN- LOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the cur- rent validity bit status ...
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... CS8427. However, certain non-audio sources, such as AC3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8427 AES3 receiver can detect such non-audio data. This is accomplished by look- ing for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F ...
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... Figure 8. Jitter Attenuation Characteristics of PLL with kHz Fs Filter Components-AES3 CFILT (µF) CRIP (nF) 2 0.047 2.2 CS8427 Digital Bode plot Frequency (Hz) PLL Lock Time (ms DS477PP3 ...
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... The CS8427 also allows immediate mute of the AES3 transmitter audio data through a control reg- ister bit. External components are used to terminate and iso- late the external cable from the CS8427. These components are detailed in AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on page Figure 9 ...
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... The “mono mode” AES3 output stream may also be achieved by keeping the CS8427 in normal ste- reo mode and placing consecutive audio samples in the left and right positions of an incoming data stream with a 48 kHz word rate ...
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... RXD1 multiplexer; RMCK is not bi-directional in this mode. DS477PP3 SIMS INC RMCKF MUX 1 0 CHANNEL STATUS ÷ PLL MEMORY USER BIT SWCLK MEMORY UNLOCK 0 MUX 1 RXD1 Figure 10. CS8427 Clock Routing CS8427 SERIAL SDOUT AUDIO OSCLK OUTPUT OLRCK TXN AES3 TRANSMIT TXP OUTC MUX 1 0 ÷ OMCK CLK[1:0] 21 ...
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... AES3 TXN Rx & I SCLK Decode TXP SD IN OUTC: 0 INC: 1 RXD1-0: 00 Figure 14. Input Serial Port to AES3 Transmitter NOTE : In this mode, ILRCK and ISCLK are in- puts only. CS8427 AES3 Serial Rx & Audio Decode Output PLL RMCK Clock Source Control Bits TXD1-0: 10 OUTC: 1 SPD1-0: 10 ...
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... Data [3]* AES3 Transmitter in Mono Mode if SILRPOL =1. if SILRPOL =1. VCU[3] VCU[4] Data [7] Data [8] Data [3] X Data [4] Tsetup => 7.5% AES3 frame time Thold = 0 Tth > 3OMCK if TCBL is Input U[2] Data [7] Data [8] X Data [4]* X Data [5]* Tsetup => 15% AES3 frame time Thold = 0 Tth > 3OMCK if TCBL is Input CS8427 23 ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit 24 Left LSB MSB LSB MSB Left MSB LSB SISF* SIRES*[1:0] X 00 Figure 17. Serial Audio Input Example Formats Right LSB Right LSB MSB Right MSB LSB SIJUST* SIDEL* SISPOL CS8427 MSB MSB SILRPOL DS477PP3 ...
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... LSB SOSF* SORES[1:0]* SOJUST Figure 18. Serial Audio Output Example Formats Right LSB MSB Right LSB MSB Right MSB LSB Right MSB SODEL* SOSPOL* SOLRPOL CS8427 MSB LSB ...
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... CS8427 is being reset. The upper four bits of the seven bit address field are fixed at 0010. To communicate with a CS8427, the chip address field, which is the first byte sent to the CS8427, should be 0010 followed by the settings of the EM- PH, AD1, and AD0. The eighth bit of the address is the R/W bit ...
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... MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit, ACK, which is output from the CS8427 after each input byte is read. The ACK bit is input to the CS8427 from the microcontroller af- ter each transmitted byte. The Two-Wire Mode is ...
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... INCR - Auto Increment Address Control Bit Default = ‘0’ Disable 1 - Enable MAP6:MAP0 - Register address Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8427 ...
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... RMCKF - Select recovered master clock output pin frequency. Default = ‘0’ RMCK is equal to 256 * Fsi 1 - RMCK is equal to 128 * Fsi MMR - Select AES3 receiver mono or stereo operation DS477PP3 MUTEAES HOLD0 RMCKF MMR CS8427 INT1 INT0 TCBLD MMT MMTCS MMTLR 29 ...
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... TXD1:TXD0 - AES3 Transmitter Data Source Default = ‘01’ Reserved 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved SPD1:SPD0 - Serial Audio Output Port Data Source Default = ‘10’ Reserved 01 - Serial Audio Input Port 10 - AES3 receiver 11 - Reserved AESBP TXD1 TXD0 CS8427 SPD1 SPD0 0 DS477PP3 ...
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... RUN is set to 1. CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). ...
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... V bits, the time slot normally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recovered clock SORES1 SORES0 SOJUST CS8427 SODEL SOSPOL SOLRPOL DS477PP3 ...
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... The source for this bit is true during the buffer transfer in the C bit buffer management process. RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. DS477PP3 CS8427 DETC EFTC RERR 33 ...
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... Be aware that the active level(Active High or Low) only depends on the INT[1:0] bits. These regis- ters default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DETU CS8427 EFTU QCH DETCM EFTCM RERRM DETC1 EFTC1 RERR1 DETC0 EFTC0 RERR0 DS477PP3 ...
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... Received channel status block is in consumer format 1 - Received channel status block is in professional format DS477PP3 DETUM DETU1 0 0 DETU0 AUX1 AUX0 PRO CS8427 EFTUM QCHM EFTU1 QCH1 0 EFTU0 QCH0 AUDIO COPY ORIG 35 ...
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... BIP - Bi-phase error bit. Updated on sub-frame boundaries error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error 1 - Parity error CCRC UNLOCK V CS8427 CONF BIP PAR DS477PP3 ...
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... Channel B information is displayed at EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode) DS477PP3 CCRCM UNLOCKM BSEL CBMR DETCI CS8427 CONFM BIPM PARM EFTCI CAM CHS 37 ...
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... UD - User data pin (U) direction specifier If this bit is changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). Default = ‘0’ The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK ...
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... Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible using these register addresses. 12.21 CS8427 I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID3 code for the CS8427. Permanently set to 0111 VER3:0 - CS8427 revision level. Revision A is coded as 0001 DS477PP3 ORR5 ORR4 ORR3 ...
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... Application note AN159 provides additional resources for the PLL. 9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states are reset. RST On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the H/S CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be ...
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... SDOUT OLRCK ILRCK Serial Audio Output C & U bit Data Buffer PRO/C COPY ORIG EMPH/U AUDIO/V Figure 21. Hardware Mode CS8427 Figure 15 on page Table 3 on page Table 4 on page 43 43, which define the equivalent Figure 17 on page 24 25. ISCLK SDIN Serial APMS ...
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... TCBL is an output Table 3. Hardware Mode Start-up Options SOSF SORES1/0 SOJUST SISF SIRES1/0 SIJUST CS8427 Function 2 S SODEL SOSPOL SOLRPOL SIDEL SISPOL ...
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... Application note AN159 provides information about the PLL. 9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states are reset. RST On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the H/S CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be ...
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... ID Code and Revision Code The CS8427 has a register that contains a four bit code to indicate that the addressed device is a CS8427. This is useful when other CS84XX family 46 members are resident in the same system, allowing common software modules ...
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... CS8427 AES3 transmitters at the channel status block boundaries. One CS8427 must have its TCBL set to master; the others must DS477PP3 be set to slave TCBL. Alternatively, TCBL can be derived from external logic, in which case all the CS8427 devices should be set to slave TCBL. CS8427 47 ...
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... L 0.016 ∝ 0° INCHES NOM MAX 0.098 0.104 0.008 0.012 0.017 0.020 0.011 0.013 0.705 0.713 0.295 0.299 0.050 0.060 0.407 0.419 0.026 0.050 4° 8° JEDEC #: MS-013 Controlling Dimension is Millimeters CS8427 MILLIMETERS MIN NOM MAX 2.35 2.50 0.10 0.20 0.33 0.42 0.23 0.28 17.70 17.90 18.10 7.40 7.50 1.02 1.27 10.00 10.34 10.65 0.40 0.65 0° ...
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... MAX MIN -- 0.47 0.004 0.006 0.05 0.035 0.04 0.80 0.0096 0.012 0.19 0.386 BSC 9.60 BSC 0.2519 0.256 6.30 0.1732 0.177 4.30 -- 0.024 0.029 0.50 4° 8° JEDEC #: MO-153 Controlling Dimension is Millimeters END VIEW L PLANE MILLIMETERS NOM MAX -- -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6.50 4.40 4.50 -- 0.65 BSC -- 0.60 0.75 0° 4° 8° CS8427 ∝ NOTE 2 ...
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... AES3 transmitter and re- ceiver to cables and fiber-optic components. 18.1 AES3 Transmitter External Components The output drivers on the CS8427 are designed to drive both the professional and consumer interfac- es. The AES3 specification for professional/broad- cast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω ...
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... AES3 Receiver External Components The CS8427 AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input im- pedance, a 110Ω ...
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... AES3 Channel Status(C) Bit Management The CS8427 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAMs through the control port ...
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... transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8427, and does not have to be written into the last byte of the block by the host microcontroller. 19.1.2 Reserving the first 5 bytes in the E ...
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... E buffer this mode, a read will cause the CS8427 to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. ...
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Notes • ...
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