24LC080-IP MicrochipTechnology, 24LC080-IP Datasheet

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24LC080-IP

Manufacturer Part Number
24LC080-IP
Description
8K/16K2.5VSPIOBusSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet
FEATURES
• SPI modes 0,0 and 1,1
• 3 MHz Clock Rate
• Single supply with programming operation down
• Low Power CMOS Technology
• Organization
• 16 Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
• Built-in Write Protection
• High Reliability
• 8-pin PDIP/SOIC Packages
• Temperature ranges supported
DESCRIPTION
The Microchip Technology Inc. 25LC080/160 are 8K
and 16K bit Serial Electrically Erasable PROMs. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also, write
operations to the Status Register can be disabled via
the write protect pin (WP).
SPI is a trademark of Motorola.
1996 Microchip Technology Inc.
to 2.5V
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1 A typical
- 1024 x 8 for 25LC080
- 2048 x 8 for 25LC160
- Protect none, 1/4, 1/2, or all of Array
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
- Commercial (C):
- Industrial (I):
8K/16K 2.5V SPI Bus Serial EEPROM
-40 C to
0 C to
This document was created with FrameMaker 4 0 4
+70 C
+85 C
Preliminary
25LC080/160
PACKAGE TYPES
BLOCK DIAGRAM
HOLD
SOIC
PDIP
SCK
WP
SO
CS
SI
I/O Control
WP
SO
V
CS
Register
Status
WP
SS
SO
V
Logic
CS
SS
Vcc
Vss
1
2
3
4
1
2
3
4
Memory
Control
Logic
8
7
6
5
Dec
8
7
6
5
X
DS21145D-page 1
Y Decoder
Sense Amp.
R/W Control
V
HOLD
SCK
SI
HV Generator
CC
V
HOLD
SCK
SI
Page Latches
EEPROM
CC
Array

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24LC080-IP Summary of contents

Page 1

... DESCRIPTION The Microchip Technology Inc. 25LC080/160 are 8K and 16K bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus ...

Page 2

ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ........................................................................ 7.0V CC All inputs and outputs w.r.t. V ......-0. Storage temperature .............................-65˚C to 150˚C Ambient temperature under bias...........-65˚C to 125˚C Soldering temperature of leads (10 seconds) ...+300˚C ESD ...

Page 3

FIGURE 1-2: SERIAL INPUT TIMING CS t CSS SCK MSB in SO FIGURE 1-3: SERIAL OUTPUT TIMING SCK t V MSB out SO SI FIGURE 1-4: HOLD TIMING CS t SCK SO ...

Page 4

TABLE 1-3: AC CHARACTERISTICS Applicable over recommended operating ranges shown below unless otherwise noted +2.5V to +5.5V CC Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Symbol Parameter f Clock Frequency ...

Page 5

... Read status register 0000 0001 Write status register (write protect enable and block write pro- tection bits) 0000 0011 Read data from memory array begin- ning at selected address 0000 0010 Write data to memory array beginning at selected address DS21145D-page 5 ...

Page 6

TABLE 2-2: WRITE PROTECT FUNCTIONALITY MATRIX WPEN WP WEL Low 0 1 Low 1 X High 0 X High 1 FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART CS Returns High ...

Page 7

... While the write is in progress, the status register may be read to check the status of the WPEN, WIP, WEL, BP1, and BP0 bits. A read attempt of a memory array location will not be possible during a write cycle. When a write cycle is completed, the write enable latch is reset 3 ...

Page 8

FIGURE 3-1: READ SEQUENCE SCK INSTRUCTION HIGH IMPEDANCE SO FIGURE 3-2: WRITE ENABLE SEQUENCE CS SCK SI SO FIGURE 3-3: WRITE SEQUENCE ...

Page 9

FIGURE 3-4: PAGE WRITE SEQUENCE SCK instruction SCK data byte ...

Page 10

PIN DESCRIPTIONS 4.1 Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be ...

Page 11

Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 25LC080/160 - /P Package: Temperature Range: Device: Sales and ...

Page 12

W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 ...

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