24LC128EP MicrochipTechnology, 24LC128EP Datasheet

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24LC128EP

Manufacturer Part Number
24LC128EP
Description
128KI2CCMOSSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet
DEVICE SELECTION TABLE
FEATURES
• Low power CMOS technology
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC (150 and 208 mil) packages
• 14-pin TSSOP package
• Temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24AA128/24LC128
(24xx128*) is a 16K x 8 (128K bit) Serial Electrically
Erasable PROM, capable of operation across a broad
voltage range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 64 bytes of data.
This device is capable of both random and sequential
reads up to the 128K boundary. Functional address
lines allow up to eight devices on the same bus, for up
to 1M bit address space. This device is available in the
standard 8-pin plastic DIP, 8-pin SOIC (150 and
208 mil), and 14-pin TSSOP packages.
I
*24xx128 is used in this document as a generic part number for the 24AA128/24LC128 devices.
M
2
C is a trademark of Philips Corporation.
100 kHz for V
100 kHz for E temperature range.
24AA128
24LC128
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 A at 5.5V
- Standby current 100 nA typical at 5.5V
- Industrial (I):
- Automotive (E):
1998 Microchip Technology Inc.
Number
Part
CC
1.8-5.5V
2.5-5.5V
Range
V
< 2.5V.
CC
128K I
-40 C to
-40 C to +125 C
Frequency
Max Clock
400 kHz
400 kHz
2
C compatible
2
+85 C
C
Ranges
Temp
CMOS Serial EEPROM
I, E
I
24AA128/24LC128
PACKAGE TYPE
BLOCK DIAGRAM
PDIP
SOIC
TSSOP
SDA
I/O
V
V
CONTROL
CC
SS
LOGIC
I/O
SCL
A0…A2
Vss
V
A0
A1
A2
A0
A1
A2
Vss
SS
NC
NC
NC
A0
A1
A2
CONTROL
MEMORY
LOGIC
1
2
3
4
WP
1
2
3
4
5
6
7
1
2
3
4
XDEC
14
13
12
11
10
9
8
8
7
6
5
8
7
6
5
DS21191B-page 1
Vcc
WP
NC
NC
NC
SCL
SDA
HV GENERATOR
PAGE LATCHES
R/W CONTROL
V
WP
SCL
SDA
Vcc
WP
SCL
SDA
SENSE AMP
CC
EEPROM
ARRAY
YDEC

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24LC128EP Summary of contents

Page 1

... SDA SCL SDA Vcc SCL 8 7 Vss SDA WP HV GENERATOR MEMORY EEPROM CONTROL XDEC ARRAY LOGIC PAGE LATCHES YDEC SENSE AMP R/W CONTROL DS21191B-page 1 ...

Page 2

ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V .................................................................................................7.0V CC All inputs and outputs w.r.t. V ............................. -0. Storage temperature ...................................................- +150 C Ambient temp. with power applied...............................- +125 C Soldering temperature of ...

Page 3

TABLE 1-3 AC CHARACTERISTICS All parameters apply across the spec- Industrial (I): ified operating ranges unless other- Automotive (E): V wise noted. Parameter Symbol Clock frequency F Clock high time T Clock low time T SDA and SCL rise time ...

Page 4

... This pin can be connected to either V floating. An internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. If tied left floating, normal memory operation SS is enabled (read/write the entire memory 0000-3FFF). If tied WRITE operations are inhibited. Read CC operations are not affected. 3.0 ...

Page 5

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) SCL SDA START CONDITION ACKNOWLEDGE FIGURE 4-2: ACKNOWLEDGE TIMING SCL SDA Data from transmitter Transmitter must release the SDA line at this point allowing the ...

Page 6

DEVICE ADDRESSING A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24xx128 this is set as 1010 binary ...

Page 7

... But instead of generating a stop condi- tion, the master transmits additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the six lower address pointer bits are internally incremented by one ...

Page 8

ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput.) Once the stop condition for a ...

Page 9

... Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24xx128 as part of a write operation (R/W bit set to 0). ...

Page 10

NOTES: DS21191B-page 10 1998 Microchip Technology Inc. ...

Page 11

PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24xx128 — /P Package: Temperature Range: Device: Sales and Support Data Sheets Products supported by a preliminary ...

Page 12

M W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: ...

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