24LC21A-IP MicrochipTechnology, 24LC21A-IP Datasheet - Page 4

• Manufacturer Part Number: 24LC21A-IP
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

24LC21A
2.0
The 24LC21A is designed to comply to the DDC Stan-
dard proposed by VESA (Figure 3-3) with the exception
that it is not Access.bus capable. It operates in two
modes, the Transmit-Only Mode and the Bi-directional
Mode. There is a separate 2-wire protocol to support
each mode, each having a separate clock input but
sharing a common data line (SDA). The device enters
the Transmit-Only Mode upon power-up. In this mode,
the device transmits data bits on the SDA pin in
response to a clock signal on the VCLK pin. The device
will remain in this mode until a valid high to low transi-
tion is placed on the SCL input. When a valid transition
on SCL is recognized, the device will switch into the Bi-
directional Mode and look for its control byte to be sent
by the master. If it detects its control byte, it will stay in
the Bi-directional Mode. Otherwise, it will revert to the
Transmit-Only Mode after it sees 128 VCLK pulses.
2.1
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the Trans-
FIGURE 2-1:
FIGURE 2-2:
DS21160B-page 4
FUNCTIONAL DESCRIPTION
Transmit-Only Mode
VCLK
VCLK
SDA
SCL
Vcc
SCL
SDA
TRANSMIT-ONLY MODE
DEVICE INITIALIZATION
Tvaa
High Impedance for 9 clock cycles
Tvhigh
Tvpu
1
Bit 1 (LSB)
Tvlow
2
Tvaa
Preliminary
Null Bit
8
mit-Only Mode (Section 2.2).
transmitted on the SDA pin in 8-bit bytes, with each byte
followed by a ninth, null bit (Figure 2-1). The clock
source for the Transmit-Only Mode is provided on the
VCLK pin, and a data bit is output on the rising edge on
this pin. The eight bits in each byte are transmitted most
significant bit first. Each byte within the memory array
will be output in sequence. After address 7Fh in the
memory array is transmitted, the internal address point-
ers will wrap around to the first memory location (00h)
and continue. The Bi-directional Mode Clock (SCL) pin
must be held high for the device to remain in the
Transmit-Only Mode.
2.2
After V
Transmit-Only Mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
00h. (Figure 2-2).
9
CC
Initialization Procedure
Bit 1 (MSB)
has stabilized, the device will be in the
Tvaa
10
Bit 8
Tvaa
11
1996 Microchip Technology Inc.
Bit 7
Bit 7
In this mode, data is