M24C01 STMicroelectronics, M24C01 Datasheet - Page 5

• Manufacturer Part Number: M24C01
• Description: 16/8/4/2/1 Kbit Serial IC Bus EEPROM
• Manufacturer: STMicroelectronics

Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V
When WC=1, Device Select and Address bytes
are
acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001 . Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
Table 4. Operating Modes
Note: 1. X =
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
IL
, and write operations are allowed.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent high significant bits of the address.
acknowledged,
V
Mode
IH
or V
IL
.
Data
IL
b7
1
1
1
1
1
) or disable (WC=V
RW bit
1
Device Type Identifier
bytes
1
0
1
1
0
0
b6
0
0
0
0
0
2
C protocol.
are
WC
V
V
X
X
X
X
IL
IL
b5
1
1
1
1
1
not
1
IH
)
M24C16, M24C08, M24C04, M24C02, M24C01
device
communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state.
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9
Bytes
b4
0
0
0
0
0
1
1
1
16
1
is
A
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
A10
E2
E2
E2
E2
b3
always
STOP
monitors
Chip Enable
Initial Sequence
E1
E1
E1
A9
A9
b2
a
condition
slave
(except
E0
E0
A8
A8
A8
b1
device
during
terminates
RW
RW
RW
RW
RW
RW
in
b0
5/20
all
th
a