M95256-RBN6T ST Microelectronics, M95256-RBN6T Datasheet - Page 8

• Manufacturer Part Number: M95256-RBN6T
• Description: 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: ST Microelectronics

M95256, M95128
Figure 9. Read EEPROM Array Operation Sequence
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
Note: 1. b15 is Don’t Care on the M95256 series.
appropriate area of the memory. When it has
finished, the appropriate values are written to the
BP1, BP0 and SRWD bits, thereby putting the
device in the hardware protected mode.
An alternative method is to write the protected
data, and to set the BP1, BP0 and SRWD bits,
before soldering the memory device to the board.
Again, this results in the memory device being
placed in its hardware protected mode.
If the W pin has been connected to V
down resistor, the memory device can be taken
Figure 10. Write Enable Latch Sequence
8/21
Address Bits
Device
b15 and b14 are Don’t Care on the M95128 series.
S
C
D
Q
0
M95256
A14-A0
S
C
D
Q
1
HIGH IMPEDANCE
INSTRUCTION
2
3
4
5
SS
M95128
A13-A0
6
by a pull-
HIGH IMPEDANCE
7
0
15
8
1
INSTRUCTION
14 13
9 10
2
16 BIT ADDRESS
3
4
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to V
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The
serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected
address, is shifted out on the Q output pin. Each
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 9. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
3
20 21 22 23 24 25 26 27
5
2
6
1
7
0
MSB
7
6
AI02281B
5
DATA OUT
4
3
28 29 30
2
1
0
AI01793
SS
,