M28W640 STMicroelectronics, M28W640 Datasheet - Page 5

• Manufacturer Part Number: M28W640
• Description: 64 Mbit 4Mb x16/ Boot Block 3V Supply Flash Memory
• Manufacturer: STMicroelectronics

SUMMARY DESCRIPTION
The M28W640C is a 64 Mbit (4 Mbit x 16) non-vol-
atile Flash memory that can be erased electrically
at the block level and programmed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. V
1.65V. An optional 12V V
vided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28W640C has an array of 135
blocks: 8 Parameter Blocks of 4 KWord and 127
Main Blocks of 32 KWord. M28W640CT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W640CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 5, Block Ad-
dresses.
The M28W640C features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 192 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divid-
ed into a 64 bit segment and a 128 bit segment.
The 64 bit segment contains a unique device num-
ber written by ST, while the second one is one-
time-programmable by the user. The user pro-
grammable segment can be permanently protect-
ed. The Security Block, parameter block 0, can be
permanently protected by the user. Figure 6,
shows the Security Block Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
PP
DDQ
V
PPLK
allows to drive the I/O pin down to
all blocks are protected against
PP
power supply is pro-
The memory is offered in TSOP48 (12 X 20mm)
and TFBGA48 (0.75mm pitch) packages and is
supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A21
DQ0-DQ15
E
G
W
RP
WP
V
V
V
V
NC
DD
DDQ
PP
SS
A0-A21
WP
RP
W
G
E
22
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Core Power Supply
Power Supply for
Input/Output
Optional Supply Voltage for
Fast Program & Erase
Ground
Not Connected Internally
V DD
M28W640CT, M28W640CB
V SS
M28W640CT
M28W640CB
V DDQ V PP
16
DQ0-DQ15
AI04378
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