DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 5

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

SUMMARY DESCRIPTION
The DSM2150F5V is an 8 or 16-bit system mem-
ory device for use with the Analog Devices DSPs.
DSM means Digital signal processor System
Memory. A DSM device brings In-System Pro-
grammable (ISP) Flash memory, parameter stor-
age, programmable logic, and additional I/O to
DSP systems. The result is a flexible two-chip so-
lution for DSP designs. On-chip integrated memo-
ry decode logic makes it easy to map dual banks
of Flash memory to the DSPs in a variety of ways
for bootloading or bypassing DSP boot ROM, code
execution, data recording, code swapping, and
parameter storage.
JTAG ISP reduces development time, simplifies
manufacturing flow, and lowers the cost of field up-
grades. The JTAG ISP interface eliminates the
need for sockets and pre-programmed memory
and logic devices. End products may be manufac-
tured with a blank DSM device soldered down and
programmed at the end of the assembly line in 15
to 35 seconds with no involvement of the DSP.
Rapidly program test code, then application code
as determined by Just-In Time inventory require-
ments. Additionally, JTAG ISP reduces develop-
ment time by turning fast iterations of DSP code in
the lab. Code updates in the field require no prod-
uct disassembly. The FlashLINK
ming cable costs $59 USD and plugs into any PC
parallel port. Programming through conventional
device insertion programmers is also available us-
ing PSDpro from STMicroelectronics and other 3rd
party programmers. See www.st.com/psm.
Figure 2. System Block Diagram, Two Chip Solution
DEVICE
DEVICE
SDRAM
SERIAL
SERIAL
HOST
I/O FLAGS
MCU
ADSP-TS101S
ADSP-2153x
ADSP-2106x
ADSP-2116x
ADSP-218x
ADSP-219x
DEVICES
ANALOG
DSP
JTAG DEBUG (All But ADSP-218x Family)
™
8 or 16 DATA
ADDRESS
CONTROL
JTAG program-
POWER MANAGEMENT
16 MACROCELL PLD
DSP SYSTEM MEMORY
CONTENT SECURITY
I/O CONTROL
FLASH MEMORY
FLASH MEMORY
DSM2150F5V
DSM devices add programmable logic (PLD) and
up to 32 configurable I/O pins to the DSP system.
The state of I/O pins can be driven by DSP soft-
ware or PLD logic. PLD and I/O configuration are
programmable by JTAG ISP. The PLD consists of
more than 3000 gates and has 16 macro cell reg-
isters. Common uses for the PLD include chip-se-
lects for external devices, state-machines, simple
shiftier and counters, keypad and control panel in-
terfaces, clock dividers, handshake delay, muxes,
etc., eliminating the need for small external PLDs
and logic devices. Configuration of PLD, I/O, and
Flash memory mapping is easily entered in a
point-and-click environment using the software
development tool, PSDsoft Express
no charge from www.st.com/psm. The two-chip
DSP/DSM combination is ideal for systems having
limitations on size, EMI levels, and power con-
sumption. DSM memory and logic are “zero-pow-
er”, meaning they automatically go to standby
between memory accesses or logic input chang-
es, producing low active and standby current con-
sumption, which is ideal for battery powered
products.
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memories and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again. The DSP will always have
access to Flash memory contents through the data
bus, even with security bit set.
SECONDARY
512 Kbytes
32 Kbytes
PRIMARY
PORTS
PORTS
AREAS
8 to 16
ISP TO
16 I/O
JTAG
WITH
PLD
ALL
I/O
I/O, PLD, CHIP SELECTS
GENERAL PURPOSE I/O
DSM2150F5V
JTAG ISP
™
, available at
AI05732
5/73