PA7540J-15 ETC, PA7540J-15 Datasheet

PA7540J-15

Manufacturer Part Number

PA7540J-15

Description

PA7540 PEEL Array Programmable Electrically Erasable Logic Array

Manufacturer

ETC

Datasheet

1.PA7540J-15.pdf (10 pages)

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Most Powerful 24-pin PLD Available

Ideal for Combinatorial, Synchronous and

High-Speed Commercial and Industrial Versions

The PA7540 is a member of the Programmable Electrically

Erasable Logic (PEEL™) Array family based on ICT’s

CMOS

designers from the limitations of ordinary PLDs by

providing the architectural flexibility and speed needed for

today’s programmable logic designs. The PA7540 is by far

the most powerful 24-pin PLD available today with 20 I/O

pins, 2 input/global-clocks and 40 registers/latches (20

buried logic cells and 20 I/O registers/latches). Its logic

array implements 84 sum-of-products logic functions. The

PA7540’s logic and I/O cells (LCCs, IOCs) are extremely

flexible offering two output functions per cell (a total of 40

for all 20 logic cells). Logic cells are configurable as D, T,

and JK registers with independent or global clocks, resets,

Figure 1. Pin Configuration

General Description

- 20 I/Os, 2 inputs/clocks, 40 registers/latches

- 40 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

Asynchronous Logic Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, multiplexers and other wide-

- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (f

- Industrial grade available for 4.5 to 5.5V V

gate functions

-40 to +85 °C temperatures

PLCC -J

I/O

N C

I/O

I/C LK1

G N D

DIP

EEPROM

I/O

1 0

1 1

1 2 1 3 1 4 1 5 1 6 1 71 8

1 0

1 1

1 2

2 8 2 7 2 6

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

2 5

2 4

2 3

2 2

2 1

2 0

1 9

technology.

VC C

I/O

I/C LK2

I/O

N C

I/O

Programmable Electrically Erasable Logic Array

I/O

N C

I/O

I/C LK1

G N D

I/O

1 0

1 1

1 2 1 3 1 4 1 5 1 6 1 7 1 8

1 0

1 1

1 2

PEEL™

1 2 8 2 7 2 6

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

PA7540 PEEL Array™

2 5

2 4

2 3

2 2

2 1

2 0

1 9

SO IC

VC C

I/O

I/C LK2

PLCC -JN

08-14-001B

I/O

N C

I/O

Arrays

MAX

and

)

free

I/C L K 1

Figure 2. Block Diagram

G N D

I/O

L o g ic C o n tro l C e lls

G lo b a l C e lls

CMOS Electrically Erasable Technology

Flexible Logic Cell

Development and Programmer Support

presets, clock polarity, and other features, making the

PA7540

synchronous and asynchronous logic applications. With pin

compatibility and super-set functionality to most 24-pin

PLDs, (22V10, EP610/630, GAL6002), the PA7540 can

implement designs that exceed the architectures of such

devices. The PA7540 supports speeds as fast as

10ns/15ns (tpdi/tpdx) and 71.46MHz (f

power consumption 80mA (55mA typical). Packaging

includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure

1). Anachip and popular third-party development tool

manufacturers provide development and programming

support for the PA7540.

PA7540

- Reprogrammable in 24-pin DIP, SOIC and

- Optional JN package for 22V10 power/ground

- 2 output functions per logic cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets,

- Sum-of-products logic for output enables

- Anachip’s WinPLACE Development Software

- Fitters for ABEL, CUPL and other software

- Programming support by popular third-party

28-pin PLCC packages

compatibility

clock polarity and output enables

programmers

I/O C e lls

2 Input/

G lobal C lock P ins

suitable

VC C

I/O

I/C L K 2

4 sum term s

4 product term s

for G lobal C ells

for

G lobal

C ells

L o g ic

A rray

80 sum term s

(four per LC C )

variety

84 (42X2)

A rray Inputs

true and

com plem ent

C ontrol

(LC C )

Logic

C ells

20 Logic C ontrol Cells

2 output functions per cell

(40 total output functions possible)

MAX

B uried

logic

) at moderate

combinatorial,

(IO C )

C ells

I/O

04-02-051B

Logic functions

to I/O cells

0 8 -1 4 -0 02 A

20 I/O P ins

Related parts for PA7540J-15

PA7540J-15 Summary of contents

Page 1

Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for ...

Page 2

Inside the Logic Array The heart of the PEEL™ Array architecture is based on a logic array structure similar to that of a PLA (programmable AND, programmable OR). The logic array implements all logic functions and provides interconnection and control ...

Page 3

Sum Sum-A Sum-B = Preset Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable after clocked Best for ...

Page 4

Input with optional register/latch Figure 8. LCC & IOC With Two Outputs Global Cells The global cells, shown in Figure 9, are used to direct global clock signals and/or control ...

Page 5

Programming of PEEL™ Arrays is supported by many popular third party programmers. Design Security and Signature Word The PEEL™ Arrays provide a special EEPROM security bit that prevents unauthorized reading or copying of designs. Once set, the programmed bits ...

Page 6

Table 1. Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin Output Current O T Storage Temperature ST T Lead Temperature LT Table 2. Operating Ranges Symbol Parameter V ...

Page 7

Table 4. A.C Electrical Characteristics Combinatorial Symbol Propagation delay Internal (t t PDI Propagation delay External (t t PDX Input or I/O pin to array input t IA Array input to LCC t AL LCC input to LCC output t ...

Page 8

Table 5. A.C. Electrical Characteristics Sequential Symbol Internal set-up to system clock t SCI ( Input (EXT.) set-up to system clock, - LCC (t t SCX System-clock to Array Int. - LCC/IOC/INC t ...

Page 9

Figure 15. Sequential Timing – Waveforms and Block Diagram Notes 1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for periods less than 20ns. 2.Test points for Clock and ...

Page 10

... Table 6. Ordering Information Part Number PA7540P-15 PA7540J-15 PA7540JN-15 PA7540S-15 PA7540PI-15 PA7540JI-15 PA7540JNI-15 PA7540SI-15 Figure 16. Part Number P ackag 300m il DIP J = Plastic (J) Leaded Chip Carrier (PLCC PLCC Alternate Pin Out S = SOIC 300 m il Gullwing Anachip USA, Inc. 780 Montague Expressway, #201 San Jose, CA 95131 ...

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