XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 10

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XQ2V3000

Manufacturer Part Number
XQ2V3000
Description
QPro Virtex-II 1.5V Military QML Platform FPGAs
Manufacturer
Xilinx
Datasheet

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Input/Output Individual Options
Each device pad has optional pull-up and pull-down resis-
tors in all SelectI/O-Ultra configurations. Each device pad
has an optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in
10
registers
Shared
by all
Program
(O/T) CLK1
(O/T) CLK2
Delay
(O/T) CE
(O/T) 1
(O/T) 2
REV
SR
OBUF
Figure 6: LVTTL, LVCMOS, or PCI SelectI/O-Ultra Standards
Program Current
Figure 5: Register/Latch Configuration in an IOB Block
V CCO
IBUF
V CCO
Figure
Clamp
Diode
D1
CE
CK1
D2
CE
CK2
SR REV
SR REV
www.xilinx.com
FF
LATCH
FF
LATCH
1-800-255-7778
6.
Q1
Q2
10-60KΩ
10-60KΩ
Attribute INIT1
Attribute INIT1
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ , which is the specification for V
when operating at 3.3V (from 3.0V to 3.6V only). The clamp
diode is always present, even when power is not.
DDR MUX
FF1
FF2
V CCO
INIT0
SRHIGH
SRLOW
INIT0
SRHIGH
SRLOW
Keeper
Weak
Reset Type
SYNC
ASYNC
DS122 (v1.1) January 7, 2004
DS031_25_110300
(OQ or TQ)
V CCAUX = 3.3V
V CCINT = 1.5V
Product Specification
DS031_23_011601
PAD
CCO
R

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