XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 37

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

Phase Shifting
The DCM provides additional control over clock skew
through either coarse- or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.
Two separate components of the phase shift range must be
understood:
•
•
The
equation:
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under
ing
Absolute range (fixed mode) = ±
Absolute range (variable mode) = ±
DS122 (v1.1) January 7, 2004
Product Specification
PHASE_SHIFT
FINE_SHIFT_RANGE
Phase Shift (ns) = (
Parameters.
PHASE_SHIFT
FINE_SHIFT_RANGE
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
R
Figure 47
attribute range
attribute is the numerator in the following
PHASE_SHIFT
PHASE_SHIFT
DCM timing parameter range
illustrates the effects of fine-phase
component, which represents
CLKFB
CLKIN
CLKFB
CLKIN
CLKIN
CLKFB
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
/256) * PERIOD
value can also be
Figure 47: Fine-Phase Shifting Effects
(PS/256) x PERIOD CLKIN
(PS negative)
DCM Tim-
(PS/256) x PERIOD CLKIN
CLKIN
www.xilinx.com
1-800-255-7778
(PS negative)
/2
shifting. For more information on DCM features, see the
Virtex-II User Guide (
Table 26
variable mode.
Table 26: Fine-Phase Shifting Control Pins
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•
•
•
PSINCDEC
PSEN
PSCLK
PSDONE
Control Pin
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT
QPro Virtex-II 1.5V Military QML Platform FPGAs
lists fine-phase shifting control pins, when used in
PHASE_SHIFT
(PS/256) x PERIOD CLKIN
(PS positive)
CLKIN
CLKIN
CLKIN
(PS/256) x PERIOD CLKIN
Direction
(PS positive)
is limited to
= 2 *
=
≤ 0.5 *
fixed mode is limited to
fixed mode is limited to
out
UG002
in
in
in
FINE_SHIFT_RANGE
value never changes after configu-
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
).
±
255 in either mode.
Increment or decrement
±
±
Active when completed
Enable ± phase shift
Clock for phase shift
64.
128.
DS031_48_101201
Function
, then
±
±
, then
128, and in
255, and in
, then
37