XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 72

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Miscellaneous Timing Parameters
Table 65: Miscellaneous Timing Parameters
Frequency Synthesis
Table 66: Frequency Synthesis
Parameter Cross Reference
Table 67: Parameter Cross Reference
72
Notes:
1.
2.
Time Required to Achieve LOCK
Using DLL outputs
Using CLKFX outputs
Additional lock time with fine-phase shifting
Fine-Phase Shifting
Absolute shifting range
Delay Lines
Tap delay resolution
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
“”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Specification also applies to PSCLK.
(1)
Description
Libraries Guide
CLKFX_MULTIPLY
CLKFX_DIVIDE
Attribute
www.xilinx.com
1-800-255-7778
LOCK_DLL_FINE_SHIFT
FINE_SHIFT_RANGE
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
LOCK_FX_MAX
DCM_TAP_MAX
DCM_TAP_MIN
LOCK_FX_MIN
LOCK_DLL_60
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
LOCK_DLL
Symbol
Min
2
1
Data Sheet
Constraints
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
> 60MHz
F
CLKIN
DS122 (v1.1) January 7, 2004
Product Specification
Value
120.0
Max
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
60.0
32
32
Units
ms
ms
ns
ps
ps
µs
µs
µs
µs
µs
µs
R