GAL16V8Z Lattice Semiconductor, GAL16V8Z Datasheet - Page 16

• Manufacturer Part Number: GAL16V8Z
• Description: Zero Power E2CMOS PLD
• Manufacturer: Lattice Semiconductor

An electronic signature word is provided in every GAL16V8Z/ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
NOTE: The electronic signature is included in checksum calcu-
lations. Changing the electronic signature will alter checksum.
A security cell is provided in the GAL16V8Z/ZD devices to pre-
vent unauthorized copying of the array patterns. Once pro-
grammed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-program-
ming the device, so the original configuration can never be ex-
amined once this cell is programmed. The electronic signature
data is always available to the user, regardless of the state of this
security cell.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the Development Tools Section of the Data Book).
Complete programming of the device takes only a few seconds.
Erasing of the device is transparent to the user, and is done au-
tomatically as part of the programming cycle.
The GAL16V8Z relies on its internal input detection circuitry to
put the device in to power down mode. If there is no input tran-
sition for the specified period of time, the device will go into the
power down state. Any valid input transition will put the device
back into the active state. The first rising clock transition from
power-down state only acts as a wake up signal to the device and
will not clock the data input through to the output (refer to standby
power timing waveform for more detail). Any input pulse widths
greater than 5ns at input voltage level of 1.5V will be detected as
input transition. The device will not detect any input pulse widths
less than 1ns measured at input voltage level of 1.5V as an in-
put transition.
The GAL16V8ZD uses pin 4 as the dedicated power-down signal
to put the device in to the power-down state. DPP is an active high
signal where a logic high driven on this signal puts the device into
power-down state. Input pin 4 cannot be used as a functional input
on this device.
Electronic Signature
Security Cell
Device Programming
Input Transition Detection (ITD)
Dedicated Power-Down Pin
16
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The GAL16V8Z/ZD devices includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
GAL16V8Z/ZD devices are designed with TTL level compatible
input buffers. These buffers, with their characteristically high im-
pedance, load driving logic much less than traditional bipolar de-
vices. This allows for a greater fan out from the driving logic.
GAL16V8Z/ZD input buffers have latches within the buffers. As
a result, when the device goes into standby mode the inputs will
be latched to its values prior to standby. In order to overcome the
input latches, they will have to be driven by an external source.
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins for both devices be connected to another ac-
tive input, V
munity and reduce I
Output Register Preload
Input Buffers
INPUT BUFFERS
-10
-20
-30
-40
40
30
20
10
0
Specifications GAL16V8Z
0
CC
, or GND. Doing this will tend to improve noise im-
Typical Input Characteristic
1
CC
Input Voltage (Volts)
for the device.
2
GAL16V8ZD
3
4
5