ISPGDX240VA-9B388I Lattice Semiconductor, ISPGDX240VA-9B388I Datasheet - Page 12

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ISPGDX240VA-9B388I

Manufacturer Part Number
ISPGDX240VA-9B388I
Description
In-System Programmable 3.3V Generic Digital CrosspointTM
Manufacturer
Lattice Semiconductor
Datasheet
ispGDX240VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the
GRP Delay with increased GRP loads. These deltas
External Timing Parameters (Continued)
ispGDX240VA Maximum
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 4 10
20
I/O Cell Fanout
GRP Delay vs. I/O Cell Fanout
12
30
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
Specifications ispGDX240VA
40
50
60
70

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