AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 135

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

15-0
CSR29: Current Receive Descriptor Address Upper
Bit
31-16
15-0
CSR30: Base Address of Transmit Ring Lower
Bit
31-16
15-0
CSR31: Base Address of Transmit Ring Upper
Bit
31-16
15-0
CRDAL
Name
RES
CRDAU
Name
RES
BADXL
Name
RES
BADXU
current receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
current receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Am79C971
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16 RES
15-0
CSR33: Next Transmit Descriptor Address Upper
Bit
31-16 RES
15-0
CSR34: Current Transmit Descriptor Address
Lower
Bit
31-16 RES
15-0
CSR35: Current Transmit Descriptor Address
Upper
Bit
31-16 RES
Name
NXDAL
Name
NXDAU
Name
CXDAL
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
zeros and read as undefined.
next transmit descriptor address
pointer.
Description
zeros and read as undefined.
next transmit descriptor address
pointer.
Description
zeros and read as undefined.
current transmit descriptor ad-
dress pointer.
Description
zeros and read as undefined.
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
Contains the upper 16 bits of the
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
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