AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 84

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Expansion Bus Interface
The Am79C971 controller contains an Expansion Bus
Interface that supports two different boot devices,
EPROM and Flash, as well as SRAM used as an exten-
sion to the internal FIFOs to buffer packets. The
Am79C971 controller supports Flash and EPROM de-
vices as boot devices as well as providing read/write
access to Flash or EPROM while the Am79C971 con-
troller is in STOP or in SPND or when the SRAM SIZE
bits (BCR25, bits 7-0) are set to 0. While in STOP, the
Am79C971 controller provides read/write diagnostic
access to SRAM (when present). This limitation on the
SRAM diagnostic is necessary to prevent data corrup-
tion.
The signal AS_EBOE is provided to strobe the upper 8
bits of the address into an external ‘374 (D flip-flop) ad-
dress latch. AS_EBOE is asser ted LOW during
EPROM/Flash read operations to control the OE input
of the EPROM/Flash.
The Expansion Bus Address is split into two different
bus es, EBUA _EB A[7:0] and EB DA [15:8]. Th e
EBUA_EBA[7:0] provides the least and the most signif-
icant address byte. When accessing SRAM and
EPROM/Flash the EBUA_EBA[7:0] is strobed into an
external ‘374 (D flip-flop) address latch. This consti-
tutes the most significant portion of the Expansion Bus
Addr es s. For S RAM/E PROM/Fla sh ac ces ses,
EBUA_EBA[7:0] constitutes the remaining least signif-
icant address byte. For byte oriented EPROM/Flash ac-
cesses, EBDA[15:8] constitutes the upper or middle
address byte. EBADDRU (BCR29, bits 3-0) should be
set to 0 even when not used, since EBADDRU consti-
tutes the EBUA portion of the EBUA EBA address byte
and is strobed into the external’374 address latch.
The signal EROMCS is connected to the CS/CE input
of the EPROM/Flash. The signal ERAMCS is con-
nected to the CE/CS input of the SRAM. The signal
84
MIIRXFRTGE
MIIRXFRTGD
SRDCLK
SFBD
SRD
Figure 41. Internal PHY Receive Frame Tagging
SFD
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Am79C971
EBWE is connected to the WE of the SRAM and Flash
devices.
The Expansion Data Bus is configured for 16-bit word
access during SRAM accesses and 8-bit byte access
during EPROM/Flash accesses. During SRAM ac-
cesses, EBD[7:0] provides the lower data byte while
EBDA[15:8] provides the upper data byte. During
EPROM/Flash accesses, EBD[7:0] provides the data
byte. See Figure 42.
Expansion ROM - Boot Device Access
The Am79C971 controller supports EPROM or Flash
as an Expansion ROM boot device. Both are config-
ured using the same methods and operate the same.
See the previous section on Expansion ROM transfers
to get the PCI timing and functional description of the
transfer method. The Am79C971 controller is function-
ally equivalent to the PCnet-PCI II controller with Ex-
pansion ROM. See Figure 43 and Figure 44.
The Am79C971 controller will always read four bytes for
every host Expansion ROM read access. The interface
to the Expansion Bus runs synchronous to the PCI bus
interface clock. The Am79C971 controller will start the
read operation to the Expansion ROM by driving the
upper 8 bits of the Expansion ROM address on
EBUA_EBA[7:0]. One-half clock later, AS_EBOE goes
high to allow registering of the upper address bits ex-
ternally. The upper portion of the Expansion ROM ad-
dress will be the same for all four byte read cycles.
AS_EBOE
EBUA_EBA[7:0] are driven with the upper 8 bits of the
Expansion ROM address for one more clock cycle after
AS_EBOE goes low. Next, the Am79C971 controller
starts driving the lower 8 bits of the Expansion ROM
address on EBUA_EBA[7:0].
is
Bit8
driven
..
..
..
..
Bitx Bity Bitz
high
for
one-half
20550D-44
clock,