AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 181

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

.
RLEN and TLEN
When SSIZE32 (BCR20, bit 8) is set to 0, the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are each three
bits wide. The values in these fields determine the
number of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 44. If a value other than
those listed in Table 44 is desired, CSR76 and CSR78
can be written after initialization is complete.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide, and the RLEN
and TLEN fields in the initialization block are each 4
bits wide. The values in these fields determine the
number of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 45.
If a value other than those listed in Table 45 is desired,
CSR76 and CSR78 can be written after initialization is
complete.
IADR+0Ch
IADR+00h
IADR+04h
IADR+08h
IADR+10h
IADR+14h
IADR+18h
Address
IADR+0Ah
IADR+0Ch
IADR+0Eh
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Address
31-28
TLEN
Bits
Bits 15-13
RLEN
TLEN
27-24
RES
Bits
Table 42. Initialization Block (SSIZE32 = 0)
Table 43. Initialization Block (SSIZE32 = 1)
RES
RLEN
23-20
P R E L I M I N A R Y
Bits
Bit 12
0
0
Am79C971
19-16
RES
Bits
LADRF 31-00
LADRF 63-32
RDRA 31-00
TDRA 31-00
PADR 31-00
RDRA and TDRA
RDRA and TDRA indicate where the transmit and re-
ceive descriptor rings begin. Each DRE must be lo-
cated at a 16-byte address boundary when SSIZE32 is
set to 1 (BCR20, bit 8). Each DRE must be located at
an 8-byte address boundary when SSIZE32 is set to 0
(BCR20, bit 8).
LADRF 15-00
LADRF 31-16
LADRF 47-32
LADRF 63-48
Bits 11-8
MODE 15-00
RDRA 15-00
TDRA 15-00
PADR 15-00
PADR 31-16
PADR 47-32
Table 44. R/TLEN Decoding (SSIZE32 = 0)
RES
RES
15-12
Bits
R/TLEN
000
001
010
011
100
101
110
111
11-8
Bits
Bits 7-4
PADR 47-32
MODE
RDRA 23-16
TDRA 23-16
Number of DREs
Bits
7-4
128
16
32
64
1
2
4
8
Bits 3-0
Bits
3-0
181