AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 135

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

SWSTYLE
All Other
[7:0]
00h
01h
02h
03h
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated by the Am79C978 controller.
This action is required because
the 16-bit software structures
specified by the SSIZE32 = 0 set-
ting will yield only 24 bits of ad-
dress
controller bus master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C978 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
LANCE/PCnet-ISA
controller
RES
PCnet-PCI
controller
PCnet-PCI
controller
RES
Name
Style
for
the
Table 31. Software Styles
Am79C978
Undefined
SSIZE32
Am79C978
0
1
1
1
7-0
16-bit software structures,
non-burst or burst access
RES
32-bit software structures,
non-burst or burst access
32-bit software structures,
non-burst or burst access
Undefined
Initialization Block
SWSTYLE
Entries
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C978 controller. The Soft-
ware Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
All Am79C978 controller CSR
bits and BCR bits and all descrip-
tor, buffer, and initialization block
entries not cited in Table 31 are
unaffected by the Software Style
selection and are, therefore, al-
ways fully functional as specified
in the CSR and BCR sections.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. The SW-
STYLE register will contain the
value 00h following H_RESET
and
S_RESET or STOP.
will
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst or burst access
Undefined
Descriptor Ring Entries
be
unaffected
135
by