HCC4046B STMicroelectronics, HCC4046B Datasheet - Page 2

• Manufacturer Part Number: HCC4046B
• Description: MICRMICROPOWER PHASE-LOCKED LOOP _
• Manufacturer: STMicroelectronics

HCC/HCF4046B
VCO Section
The VCO requires one external capacitor C1 and
one or two external resistors (R1 or R1 and R2). Re-
sistor R1 and capacitor C1 determine the frequency
range of the VCO and resistor R2 enables the VCO
to have a frequency offset if required. The high input
impedance (10
of low-pass filters by permitting the designer a wide
choice of resistor-to-capacitor ratios. In order not to
load the low-pass filter, a source-follower output of the
VCO input voltage is provided at terminal 10 (DE-
MODULATED OUTPUT). If this terminal is used, a
load resistor (R
nected from this terminal to V
nal should be left open. The VCO can be connected
either directly or through frequency dividers to the
comparator input of the phase comparators. A full
COS/MOSlogic swing is available at the output of the
VCO and allows direct coupling to COS/MOS fre-
quency dividers such as the HCC/HCF4024B,
HCC/HCF4018B, HCC/HCF4020B,
HCC/HCF4022B, HCC/HCF4029B,and
HBC/HBF4059A. One or more HCC/HCF4018B
(Presettable Divide-by-N Counter) or HCC/HCF4029B
(Presettable Up/Down Counter), or HBC/HBF4059A
(Programmable Divide-by-”N” Counter), together
with the HCC/HCF4046B (Phase-Locked Loop) can
be used to build a micropower low-frequency syn-
thesizer. A logic 0 on the INHIBIT input ”enables” the
VCO and the source follower, while a logic 1 ”turns
off” both to minimize stand-by power consumption.
Phase Comparators
The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within COS/MOS logic levels [logic ”0”
(V
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR net-
work ; it operates analagously to an over-driven bal-
anced mixer. To maximize the lock range, the
signal-and comparator-input frequencies must have
a 50% duty cycle. With no signal or noise on the sig-
nal input, this phase comparator has an average
output voltage equal to V
connected to the output of phase comparator I sup-
plies the averaged voltage to the VCO input, and
causes the VCO to oscillate at the center frequency
(f
the PLL will lock if it was initially out of lock is defined
as the frequency capture range (2 f
range of input signals on which the loop will stay
locked if it was initially in lock is defined as the fre-
quency lock range (2 f
2/13
o
DD
). The frequency range of input signals on which
– V
SS
), logic ”1”
12
S
) of 10 k or more should be con-
) of the VCO simplifiers the design
L
). The capture range is the
DD
70 % (V
SS
/2. The low-pass filter
. If unused this termi-
c
). The frequency
DD
- V
SS
)]. For
30 %
lock range. With phase comparator I the range of
frequencies over which the PLL can acquire lock
(capture range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lock range. Phase-comparator I enables a PLL sys-
tem to remain in lock in spite of high amounts of
noise in the input signal. One characteristic of this
type of phase comparator is that it may lock onto
input frequencies that are close to harmonics of the
VCO center-frequency. A second characteristic is
that the phase angle between the signal and the
comparator input varies between 0 and 180 , and
is 90 at the center frequency. Fig. (a) shows the
typical, triangular, phase-to-output response char-
acteristic of phase-comparator I. Typical waveforms
for a COS/MOS phase-locked-loop employing
phase comparator I in locked condition of f
in fig. (b). Phase-comparator II is an edge-controlled
digital memory network. It consists of four flip-flop
stages, control gating, and a three-stage output-cir-
cuit comprising p- and n-type drivers having a com-
mon output node. When the p-MOS or n-MOS
drivers are ON they pull the output up to V
to V
acts only on the positive edges of the signal and
comparator inputs. The duty cycles of the signal and
comparator inputs are not important since positive
transitions control the PLL system utilizing this type
of comparator. If the signal-input frequency is higher
than the comparator-input frequency, the p-type
output driver is maintained ON most of the time, and
both the n- and p-drivers OFF (3 state) the remain-
der of the time. If the signal-input frequency is lower
than the comparator-input frequency, the n-type
output driver is maintained ON most of the time, and
both the n- and p-drivers OFF (3 state) the remain-
der of the time. If the signal and comparator-input
frequencies are the same, but the signal input lags
the comparator input in phase, the n-type output
driver is maintained ON for a time corresponding to
the phase difference. If the signal and comparator-
input frequencies are the same, but the comparator
input lags the signal in phase, the p-type output
driver is maintained ON for a time corresponding to
the phase difference. Subsequently, the capacitor
voltage of the low-pass filter connected to this phase
comparator is adjusted until the signal and com-
parator inputs are equal in both phase and fre-
quency. At this stable point both p- and n-type output
drivers remain OFF and thus the phase comparator
output becomes an open circuit and holds the volt-
age on the capacitor of the low-pass filter constant.
Moreover the signal at the ”phase pulses” output is
a high level which can be used for indicating a locked
condition. Thus, for phase comparator II, no phase
difference exists between signal and comparator
SS
, respectively. This type of phase comparator
DD
o
is shown
or down