EVAL-AD7321CB AD [Analog Devices], EVAL-AD7321CB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD7321CB
• Description: 500 kSPS, 2-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

AD7321
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7321 is a fast, 2-channel, 12-bit plus sign, bipolar input,
serial A/D converter. The AD7321 can accept bipolar input
ranges that include ±10 V, ±5 V, and ±2.5 V; it can also accept a
0 V to +10 V unipolar input range. A different analog input
range can be programmed on each analog input channel via the
on-chip registers. The AD7321 has a high speed serial interface
that can operate at throughput rates up to 500 kSPS.
The AD7321 requires V
voltage analog input structures. These supplies must be equal to
or greater than the largest analog input range selected. See Table 6
for the requirements of these supplies for each analog input range.
The AD7321 requires a low voltage 2.7 V to 5.25 V V
to power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog
Input Range
(V)
±10
± 5
±2.5
0 to +10
It may be necessary to decrease the throughput rate when the
AD7321 is configured with the minimum V
in order to meet the performance specifications (see the
Performance Characteristics section). Figure 31 shows the
change in THD as the V
performance at the maximum throughput rate, the THD degrades
slightly as V
to reduce the throughput rate when using minimum V
V
specified performance can be maintained. The degradation is
due to an increase in the on resistance of the input multiplexer
when the V
Figure 19 show the change in INL and DNL as the V
voltages are varied. For dc performance when operating at the
maximum throughput rate, as the V
are reduced, the typical INL and DNL error remains constant.
SS
supplies so that there is less degradation of THD and the
DD
DD
and V
and V
Reference
Voltage (V)
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
SS
SS
are reduced. It might therefore be necessary
supplies are reduced.
DD
DD
and V
and V
Full-
Scale
Input
Range
(V)
±10
±12
±5
±6
±2.5
±3
0 to +10
0 to +12
SS
SS
dual supplies for the high
supplies are reduced. For ac
DD
and V
AV
(V)
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
Figure 18 and
DD
SS
and V
CC
supply voltages
Minimum
V
±10
±12
±5
±6
±5
±5
+10/AGND
+12/AGND
DD
SS
CC
DD
supplies
DD
and V
/V
supply
Typical
and
SS
(V)
Rev. 0 | Page 16 of 36
SS
The analog inputs can be configured as two single-ended
inputs, one true differential input pair, or one pseudo
differential input. Selection can be made by programming the
mode bits, Mode 0 and Mode 1, in the control register.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7321 has an on-chip 2.5 V reference. However, the AD7321
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal
reference operation.
The AD7321 also features power-down options to allow power
savings between conversions. The power-down modes are
selected by programming the on-chip control register, as
described in the
CONVERTER OPERATION
The AD7321 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 23 and
Figure 24 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively.
schematics of the ADC in differential mode during acquisition
and conversion phases, respectively. The ADC is composed of
control logic, a SAR, and capacitive DACs. In
acquisition phase), SW2 is closed and SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor array acquires the signal on the input.
When the ADC starts a conversion (Figure 24), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
V
IN
0
Figure 23. ADC Acquisition Phase (Single-Ended)
Figure 25 and Figure 26 show simplified
AGND
B
A
Modes of Operation section.
SW1
C
S
SW2
COMPARATOR
CAPACITIVE
CONTROL
Figure 23 (the
LOGIC
DAC