EVAL-AD7321CB AD [Analog Devices], EVAL-AD7321CB Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD7321CB
• Description: 500 kSPS, 2-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

+15V
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7321.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7321 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7321 can operate
with either an internal or external reference. In Figure 32, the
AD7321 is configured to operate with the internal 2.5 V
reference. A 680 nF decoupling capacitor is required when
operating with the internal reference.
The V
5 V supply voltage. The V
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the V
the serial interface. V
–15V
ANALOG INPUT
Single-Ended Inputs
The AD7321 has a total of two analog inputs when operating
the AD7321 in single-ended mode. Each analog input can be
independently programmed to one of the four analog input
ranges. In applications where the signal source is high
impedance, it is recommended to buffer the signal before
applying it to the ADC analog inputs.
configuration of the AD7321 in single-ended mode.
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
CC
680nF
0.1µF
pin can be connected to either a 3 V supply voltage or a
0.1µF
+
+
Figure 32. Typical Connection Diagram
10µF
10µF
V
V
REFIN/OUT
IN
IN
0
1
V
DD
V
DRIVE
1
AD7321
SS
1
MINIMUM V
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
1
DD
can be set to 3 V or 5 V.
AGND
DRIVE
and V
V
CC
V
DGND
DOUT
SCLK
DRIVE
DD
DIN
10µF
CS
input controls the voltage of
AND V
SS
10µF
are the dual supplies for the
+
SS
Figure 33 shows the
0.1µF
SUPPLY VOLTAGES
+
Table 6). The V
0.1µF
INTERFACE
SERIAL
+3V SUPPLY
V
CC
µC/µP
+ 2.7V TO 5.25V
DRIVE
Rev. 0 | Page 19 of 36
True Differential Mode
The AD7321 can have one true differential analog input pair.
Differential signals have some benefits over single-ended
signals, including better noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance.
differential analog inputs of the AD7321.
The amplitude of the differential signal is the difference
between the signals applied to the V
each differential pair (V
be simultaneously driven by two signals each of amplitude
±4 × VREF (depending on the input range selected) that
are 180° out of phase. Assuming the ±4 × VREF mode, the
amplitude of the differential signal is −20 V to +20 V p-p
(2 × 4 × VREF), regardless of the common mode.
The common mode is the average of the two signals
and is therefore the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the V
and the V
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × VREF) to
+2 × (4 × VREF) corresponding to Digital Codes −4096 to +4095.
(V
AGND
Figure 33. Single-Ended Mode Typical Connection Diagram
IN
+ + V
SS
supply pin.
Figure 34 defines the configuration of the true
1
IN
ADDITIONAL PINS OMITTED FOR CLARITY.
−)/2
Figure 34. True Differential Inputs
1
ADDITIONAL PINS OMITTED FOR CLARITY.
IN
+ − V
V+
V–
V
V
IN
IN
IN
−). V
+
–
AD7321
IN
+ and V
IN
V
+ and V
IN
+
AD7321
1
IN
V
− pins in
V
IN
DD
SS
1
− should
DD
V
AD7321
5V
CC
supply pin