HY27SS08121A HYNIX [Hynix Semiconductor], HY27SS08121A Datasheet

HY27SS08121A

Manufacturer Part Number

HY27SS08121A

Description

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

Manufacturer

HYNIX [Hynix Semiconductor]

Datasheet

1.HY27SS08121A.pdf (49 pages)

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Document Title

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory

Revision History

Rev 1.3 / Jun. 2006

Revision

No.

0.0

0.1

0.2

Initial Draft.

1) Correct part number ( change mode)

- 2A -> 1A (sequential row read : disable -> enable)

2) Correct Table.5 & Table 12

- Correct Command Set

- correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns)

3) Correct Summary description & page.7

- The cache feature is deleted in summary description.

- Note.3 is deleted. (page.7)

4) Add System interface using CE don’t care (page. 38)

5) Change TSOP1, WSOP1,FBGA package dimension & figures.

6) Correct TSOP1, WSOP1 Pin configuration

7) Add Bad block Management

1) LOCKPRE is changed to PRE

- Texts, Table and figures are changed.

2) Change Command set

- Read A,B are changed to Read1.

- Read C is changed to Read2.

3) Change AC, DC characterics

- tRB, tCRY, tCEH and tOH are added.

4) Correct Program time (max)

- before : 700us

- after

5) Edit figures

- Address names are changed.

6) Change FBGA Package Dimension

- FD1 : 1.70(before) -> 0.90(after)

- Change TSOP1, WSOP1, FBGA package mechanical data

- Change TSOP1, WSOP package figures

- 38th NC pin has been changed Lockpre (figure 2,3)

: 500us

History

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

HY27US(08/16)121A Series

HY27SS(08/16)121A Series

Oct. 22. 2004 Preliminary

Mar. 08. 2005 Preliminary

Draft Date

Sep. 2004

Preliminary

Remark

Related parts for HY27SS08121A

HY27SS08121A Summary of contents

Page 1

Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Correct part number ( change mode -> 1A (sequential row read : disable -> enable) 2) Correct Table.5 & Table 12 ...

Page 2

Revision History Revision No. 1) Change AC Characteristics (1.8V device) tRC before 50 after 60 2) Change AC Parameter 0.3 Before After 3) Change Figure 20,22 4) Add Read ID Table 5) Change PAD Configuration - GND is changed to ...

Page 3

Revision History Revision No. 1) The test conditions is corrected. Test Conditions ( Before After 0.5 2) Change VIL parameter (max.) Before After 1) Correct the test Conditions (DC Characteristics table) VIN=VOUT=(1.8V 1.95V) Before 0.6 After VIN=VOUT=0 to ...

Page 4

Revision History Revision No. 1.0 1) Delet Preliminary. 1.1 1) Correct Figure 32. 1) Add ECC algorithm. (1bit/512bytes) 1.2 2) Correct Read ID naming 1) Change AC Parameter tWHR 1.3 Before 60 ns After 50 ns Rev 1.3 / Jun. ...

Page 5

FEATURES SUMMARY HIGH DENSITY NAND Flash MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...

Page 6

SUMMARY DESCRIPTION The HYNIX HY27(U/S)S(08/16)121A series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the ...

Page 7

IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC PRE Rev 1.3 / Jun. 2006 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 Only) Data Input / ...

Page 8

Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48USOP1 Contactions, x8 and x16 Device Rev 1.3 / Jun. 2006 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 8 ...

Page 9

Figure 4. 63FBGA Contactions, x8 Device (Top view through package) Figure 5. 63FBGA Contactions, x16 Device (Top view through package) Rev 1.3 / Jun. 2006 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 9 ...

Page 10

PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...

Page 11

IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 4th Cycle A25 NOTE must be set to Low set to LOW or High by the 00h or 01h Command. IO0 1st Cycle A0 2nd ...

Page 12

CLE ALE ( NOTE: 1. With ...

Page 13

BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...

Page 14

DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the four address input cycles. Once the ...

Page 15

Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...

Page 16

Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...

Page 17

OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V (1.8V device), 2.0V (3.3V ...

Page 18

Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 21. - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to ...

Page 19

Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles without ECC. (1bit/512bytes) Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient ...

Page 20

Rev 1.3 / Jun. 2006 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 6: Block Diagram 20 ...

Page 21

Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...

Page 22

Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of partial Program Cycles in the same page Block Erase Time Table 11: Program ...

Page 23

Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...

Page 24

... Ready/Busy 6 Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd Part Number HY27US08121A HY27US16121A HY27SS08121A HY27SS16121A Rev 1.3 / Jun. 2006 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Block Read Erase Pass / Fail Ready/Busy Ready/Busy Ready/Busy ...

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