HY27UH08AGDM HYNIX [Hynix Semiconductor], HY27UH08AGDM Datasheet
HY27UH08AGDM
Related parts for HY27UH08AGDM
HY27UH08AGDM Summary of contents
Page 1
... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Dec. 2006 HY27UH08AG5M HY27UH08AGDM HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash 1 ...
Page 2
... Document Title 16Gbit (2Gx8bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Add HY27UH08AG5M & HY27UH08AGDM Products. - Texts & figures are added. 2) Change Ac Characteristics tR Before 20 After 25 tCLS Before 12 0.1 After 15 3) Add tCRRH (100ns, Min) - tCRRH: cache Read RE# High 4) Change 3rd Read ID - 3rd Read ID is changed to C1h - 3rd Byte of Device Identifier Table is added ...
Page 3
Revision History Revision No. 0.4 1) Delete Preliminary. 0.5 1) Correct copy back function. 1) Delete PRE function. 2) Delete Lock & Unlock function. 0.6 3) Delete Auto Read function. Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND ...
Page 4
... Simple interface with microcontroller SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles (with 1bit/512byte ECC years Data Retention PACKAGE - HY27UH08AG5M-T(P) : 48-Pin TSOP1 ( 1.2 mm) - HY27UH08AG5M-T (Lead) - HY27UH08AG5M-TP (Lead Free) - HY27UH08AGDM-MP : 52-TLGA ( 1.0 mm) - HY27UH08AGDM-MP (Lead Free) ...
Page 5
... This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HYNIX HY27UH08AG(5/D)M series is available TSOP1 mm TLGA 12X17mm. 1.1 Product List PART NUMBER HY27UH08AG5M HY27UH08AGDM 2. BUS OPERATION Rev. 0.6 / Dec. 2006 16Gbit (2Gx8bit) NAND Flash ORIZATION VCC RANGE x8 2 ...
Page 6
IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip Enable Read ...
Page 7
Figure 2. 48TSOP1 Contactions, x8 Device (2CE) Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 8
Figure 3. 52-ULGA Contactions, x8 Device, Dual interface Rev. 0.6 / Dec. 2006 (Top view through package) HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 9
PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0-IO7 operations. The inputs are latched on the rising edge of Write Enable (WE). The ...
Page 10
IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 1. L must be set to Low. FUNCTION READ 1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM (start) COPY BACK PGM (start) CACHE ...
Page 11
CLE ALE ( NOTE: 1. With ...
Page 12
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read Enable are ignored ...
Page 13
DEVICE OPERATION 3.1 Page Read. Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read operations, the second one doesn’t’ need 00h command, which five address ...
Page 14
Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command (60h). Only address A18 to A30 (X8) is valid while A12 to A17 (X8) ...
Page 15
Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...
Page 16
Cache Program. Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may ...
Page 17
Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...
Page 18
OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides ...
Page 19
Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles with ECC. (1bit/512bytes) Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient ...
Page 20
Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash Figure 4: Block Diagram ...
Page 21
Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Table 8: DC ...
Page 22
... Block Erase Time Table 11: Program / Erase Characteristics Rev. 0.6 / Dec. 2006 Test Min Condition HY27UH08AG5M-T( Main Array Spare Array HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash Max HY27UH08AGDM- Symbol Min Typ Max t - 200 700 PROG 700 CBSY RBSY ...
Page 23
Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Address to Data Loading Time ...
Page 24
... Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th Part Number Voltage HY27UH08AG5M 3.3V HY27UH08AGDM 3.3V Rev. 0.6 / Dec. 2006 Cache Read Program Pass / Fail (N) NA Pass / Fail (N- P/E/R Ready/Busy Controller Bit Cache Register Ready/Busy ...
Page 25
Description 1 2 Internal Chip Number Level Cell 4 Level Cell Cell Type 8 Level Cell 16 Level Cell 1 Number of 2 Simultaneously 4 Programmed Pages 8 Interleave Program Not Support Belween multiple chips Support Not ...
Page 26
Rev. 0.6 / Dec. 2006 Figure 5: Command Latch Cycle HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 27
Rev. 0.6 / Dec. 2006 Figure 6: Address Latch Cycle Figure 7. Input Data Latch Cycle HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 28
Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 29
Figure 11: Read1 Operation (Read One Page) Rev. 0.6 / Dec. 2006 16Gbit (2Gx8bit) NAND Flash Figure 10: Status Read Cycle HY27UH08AG(5/D)M Series ...
Page 30
Figure 12: Read1 Operation intercepted by CE Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 31
Rev. 0.6 / Dec. 2006 Figure 13 : Random Data output HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 32
Rev. 0.6 / Dec. 2006 Figure 14: Page Program Operation HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 33
Rev. 0.6 / Dec. 2006 16Gbit (2Gx8bit) NAND Flash Figure 15: Random Data In HY27UH08AG(5/D)M Series ...
Page 34
Rev. 0.6 / Dec. 2006 Figure 16: Copy Back Program HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 35
Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash Figure 17: Cache Program ...
Page 36
Rev. 0.6 / Dec. 2006 Figure 18 : Cache Read RE high HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 37
Figure 19: Block Erase Operation (Erase One Block) Rev. 0.6 / Dec. 2006 16Gbit (2Gx8bit) NAND Flash Figure 20: Read ID Operation HY27UH08AG(5/D)M Series ...
Page 38
Figure 21: start address at page start :after 1st latency uninterrupted data flow Figure 22: exit from cache read in 5us when device internally is reading Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 39
System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
Page 40
Figure 26: Power On and Data Protection Timing VTH = 2.5 Volt for 3.3 Volt Supply devices Rev. 0.6 / Dec. 2006 Figure 25: Reset Operation HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 41
Figure 27: Ready/Busy Pin electrical specifications Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 42
Rev. 0.6 / Dec. 2006 Figure 28: page programming within a block HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash ...
Page 43
Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
Page 44
Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 30~33) Rev. 0.6 / Dec. 2006 Figure 30: Enable Programming Figure 31: ...
Page 45
Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash Figure 32: Enable Erasing Figure 33: Disable Erasing ...
Page 46
APPENDIX : Extra Features 5.1 Addressing for program operation Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random address programming ...
Page 47
Figure 34. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev. 0.6 / Dec. ...
Page 48
Figure 35. 52-TLGA 17mm, Package Outline Symbol CP1 CP2 Table 20g: 52-TLGA 17mm, Package Mechanical Data Rev. 0.6 / Dec. 2006 16Gbit (2Gx8bit) NAND ...
Page 49
MARKING INFORMATION - ...