EVAL-ADF9010EBZ AD [Analog Devices], EVAL-ADF9010EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADF9010EBZ
• Description: 900 MHz ISM Band Analog RF Front End
• Manufacturer: AD [Analog Devices]

CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed.
Figure 22 shows the input data format for programming
the control latch.
Power-Down
Programming a 1 to PD4, PD3, PD2, PD1 powers down
the circuitry for the Rx filters, PLL, VCO, and Tx sections,
respectively. Programming a 0 enables normal operation for
each section.
Tx Output Power
Bit TP1 and Bit TP2 set the output power level of the VCO.
See the truth table in Figure 22.
Charge Pump Current
Bit CPI3, Bit CPI2, and Bit CPI1 determine Current Setting 2.
See the truth table in Figure 22.
LO Output Power
Bit P1 and Bit P2 set the output power level of the LO. See the
truth table in Figure 22.
Mute LO Until Lock Detect
Bit F5 is the mute until lock detect bit. This function, when
enabled, ensures that the LO outputs are not switched on
until the PLL is locked.
Mute Tx Until Lock Detect
Bit F4 is the mute Tx until lock detect bit. This function, when
enabled, ensures that the Tx outputs are not switched on until
the PLL is locked.
Charge Pump Three-State
Bit F3 puts the charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
Bit F2 sets the phase detector polarity. The positive setting
enabled by programming a 1 is used when using the on-chip
VCO with a passive loop filter or with an active noninverting
filter. It can also be set to 0. This is required if an active inverting
loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Figure 22.
Counter Reset
Bit F1 is the counter reset bit for the PLL of the ADF9010.
When this bit is set to 1, the R, A, and B counters are held
in reset. For normal operation, this bit should be 0.
Reserved Bits
DB3 and DB2 are spare bits that are reserved. They should
be programmed to 0 and 1, respectively.
Rev. 0 | Page 21 of 28
Tx LATCH
With (C3, C2, C1) = (0, 0, 1), the Tx latch is programmed.
Figure 23 shows the input data format for programming
the Tx latch.
LO Phase Select
Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the
demodulator. This enables the user to select the phase delay of
the Rx LO signal to the demodulator in 90° steps. See the truth
table in Figure 23. The Rx LO output can be disabled if desired.
Tx Modulation LO Phase Select
Bit T3, Bit T2, and Bit T1 set the input modulation of the
VCO. Normal quadrature to each mixer can be replaced by
choosing one LO phase to both mixers if desired. The normal
(I) or quadrature (Q) phase can be chosen. See the truth table
in Figure 23.
Band Select Clock
Bits BSC2 and Bit BSC1 set a divider for the band select logic
clock input. The recommended setting is 1, 1, which programs
a value of 8 to the divider. No other setting is allowed.
Reference Counter
R13 to R1 set the counter divide ratio. The divide range is 1
(00 … 001) to 8191 (111 … 111).
Rx CALIBRATION LATCH
With (C3, C2, C1) = (1, 0, 1), the Rx calibration latch is
programmed. Figure 24 shows the input data format for
programming the Rx calibration latch.
LO Phase Select
Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the
demodulator. This enables the user to select the phase delay of
the Rx LO signal to the demodulator in 90° steps. See the truth
table in Figure 24. The Rx LO output can be disabled if desired.
Tx Modulation LO Phase Select
Bit T3, Bit T2, and Bit T1 set the input modulation of the VCO.
Normal quadrature to each mixer can be replaced by choosing
one LO phase to both mixers if desired. The normal (I) or quad-
rature (Q) phase can be chosen. See the truth table in Figure 24.
Band Select Clock
Bit BSC2 and Bit BSC1 set a divider for the band select logic
clock input. The recommended setting is 1, 1, which programs
a value of 8 to the divider. No other setting is allowed.
Rx Filter Calibration
Setting Bit R13 high performs a calibration of the Rx filters’
cutoff frequency, f
frequency calibration sequence is not initiated if this latch is
programmed.
C
. Setting this bit to 0 ensures the filter cutoff
ADF9010