EVAL-ADT7410EBZ AD [Analog Devices], EVAL-ADT7410EBZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-ADT7410EBZ
• Manufacturer: AD [Analog Devices]

T
The T
the overtemperature limit value. An overtemperature event
occurs when the temperature value stored in the temperature
value register exceeds the value stored in this register. The INT
pin is activated if an overtemperature event occurs. The temper-
ature is stored in twos complement format with the MSB being
the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x04 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x05. Only
Register Address 0x04 (T
into the address pointer register as the address pointer auto-
increments to Register Address 0x05 (T
The default setting for the T
T
The T
the undertemperature limit value. An undertemperature event
occurs when the temperature value stored in the temperature
value register is less than the value stored in this register. The
INT pin is activated if an undertemperature event occurs. The
temperature is stored in twos complement format with the MSB
being the temperature sign bit.
Table 12. T
Bit
[15:8]
Table 13. T
Bit
[7:0]
Table 14. T
Bit
[15:8]
Table 15. T
Bit
[7:0]
Table 16. T
Bit
[15:8]
Table 17. T
Bit
[7:0]
HIGH
LOW
SETPOINT REGISTERS
HIGH
LOW
SETPOINT REGISTERS
setpoint MSB and T
setpoint MSB and T
HIGH
HIGH
LOW
LOW
CRIT
CRIT
Default Value
0x49
0x20
Default Value
0x05
Default Value
0x80
Default Value
Default Value
0x00
Default Value
0x00
Setpoint MSB Register (Register Address 0x06)
Setpoint LSB Register (Register Address 0x07)
Setpoint MSB Register (Register Address 0x08)
Setpoint LSB Register (Register Address 0x09)
Setpoint MSB Register (Register Address 0x04)
Setpoint LSB Register (Register Address 0x05)
HIGH
HIGH
setpoint MSB) needs to be loaded
LOW
HIGH
setpoint is 64°C.
Type
R/W
Type
R/W
R/W
Type
R/W
Type
Type
R/W
Type
R/W
setpoint LSB registers store
setpoint LSB registers store
HIGH
Name
T
Name
T
Name
T
Name
T
Name
T
Name
T
LOW
CRIT
CRIT
HIGH
LOW
setpoint LSB).
HIGH
MSB
MSB
LSB
LSB
MSB
LSB
Description
LSBs of the critical overtemperature limit, stored in twos complement format.
Description
MSBs of the overtemperature limit, stored in twos complement format.
LSBs of the overtemperature limit, stored in twos complement format.
Description
Description
MSBs of the critical overtemperature limit, stored in twos complement format.
Description
LSBs of the undertemperature limit, stored in twos complement format.
MSBs of the undertemperature limit, stored in twos complement format.
Description
Rev. 0 | Page 15 of 24
When reading from this register, the eight MSBs (Bit 15 to Bit
8) are read first from Register Address 0x06 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x07. Only
the Register Address 0x06 (T
loaded into the address pointer register as the address pointer
autoincrements to Register Address 0x07 (T
The default setting for the T
T
The T
the critical overtemperature limit value. A critical overtempe-
rature event occurs when the temperature value stored in the
temperature value register exceeds the value stored in this
register. The CT pin is activated if a critical overtemperature
event occurs. The temperature is stored in twos complement
format with the MSB being the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x08 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x09.
Only the Register Address 0x08 (T
be loaded into the address pointer register as the address pointer
autoincrements to Register Address 0x09 (T
The default setting for the T
CRIT
SETPOINT REGISTERS
CRIT
setpoint MSB and T
CRIT
LOW
LOW
CRIT
limit is 147°C.
setpoint is 10°C.
setpoint MSB) needs to be
setpoint LSB registers store
CRIT
setpoint MSB) needs to
LOW
CRIT
setpoint LSB).
setpoint LSB).
ADT7410